共查询到20条相似文献,搜索用时 31 毫秒
1.
N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V t shift due to irradiation of the hot-electron stressed (stressing with V d=V g=6.5 V) device was less than that of the unstressed device 相似文献
2.
Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I sub condition (V g =0.5 V d). However, in the high-gate-bias region (V g=V d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V g>V d), this current-crowding effect in the diagonal transistor can be a serious reliability concern 相似文献
3.
《Electron Devices, IEEE Transactions on》1990,37(1):153-158
The fabrication of a silicon heterojunction microwave bipolar transistor with an n+ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V CE=6 V, I c=15 mA), and an emitter Gummel number G E of about 1.4×1014 Scm-4. From the measured S parameters, a cutoff frequency f t of 5.5 GHz and maximum oscillating frequency f max of 7.5 GHz at V CE=10 V, I c=10 mA are obtained 相似文献
4.
Busta H.H. Pogemiller J.E. Zimmerman B.J. 《Electron Devices, IEEE Transactions on》1993,40(8):1537-1542
The field at the tip of a field emitter triode can be expressed by E =βV g+γV c, where V g and V c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, γV c<<βV g. The-device is operated in the gate-induced field emission mode and the corresponding I -V c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I -V c and transconductance g m-V g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly 相似文献
5.
Scherrer D. Kruse J. Laskar J. Feng M. Wada M. Takano C. Kasahara J. 《Electron Device Letters, IEEE》1993,14(9):428-430
The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5-μm×100-μm E-JFET with a threshold voltage of V th=0.3 V achieved a maximum DC transconductance of g m=489 mS/mm at V ds=1.5 V and I ds=18 mA. Operating at 0.5 mW of power with V ds=0.5 V and I ds =1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F min=1.2 dB and the average associated gain was G a=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications 相似文献
6.
Hot-carrier degradation of W gate PMOSFETs, which are surface-channel devices because of the work function of W, has been investigated in comparison with polycide (WSix/n+ poly-Si) ones. In W gate PMOSFETs, transconductance g m and threshold voltage V th decrease on the drain avalanche hot-carrier (DAHC) stress, and Δg m /g m0 and ΔV th become minimum at V G≅V D/2. By using the charge-pumping technique, it is found that, after stressing at the same stress condition, the interface state density of W gate devices is about 10 times larger than that of polycide ones but the densities of trapped electrons are almost equal. These results indicate that the difference of hot-carrier degradation between W and polycide gate devices is mainly caused by the difference of the interface state density 相似文献
7.
Vuillaume D. Marchetaux J.-C. Lippens P.-E. Bravaix A. Boudou A. 《Electron Devices, IEEE Transactions on》1993,40(4):773-781
The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V d/8 to V d) by hot-hole and/or hot-electron injections, and their generation rates (10-9 and 10-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I d-V g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I d-V g degradation 相似文献
8.
Hida H. Tsukada Y. Ogawa Y. Toyoshima H. Fujii M. Shibahara K. Kohno M. Nozaki T. 《Electron Devices, IEEE Transactions on》1989,36(10):2223-2230
The authors describe a novel design concept for enhancement (E) and depletion (D) mode FET formation using i-AlGaAs/n-GaAs doped-channel hetero-MISFET (DMT) and a novel self-aligned gate process technology for submicrometer-gate DMT-LSIs based on E/D logic gates. 0.5-μm gate E-DMTs (D-DMTs) with a lightly doped drain (LDD) structure show an average V t of 0.18 (-0.46) V, a V t standard deviation of 22.6 (24.9) mV, and a maximum transconductance of 450 (300) mS/mm. The V t shift is less than 50 mV with a decrease in gate length down to 0.5 μm. The gate forward turn-on voltage V f is more than 0.9 V, i.e. about 1.6 times that for MESFETs. This superiority in V f, preserved in the high-temperature range, leads to an improvement in noise margin tolerance by a factor of three. In addition, 31-stage ring oscillators operate with a power consumption of 20 (1.0) mW/gate and a propagation delay of 4.8 (14.5) ps/gate. Circuit simulation based on the experimental data predicts 140 ps/gate and 1 mW/gate for DMT direct-coupled FET logic circuits under standard loading conditions. DMTs and the technology developed here are very attractive for realizing low-power and/or high speed LSIs 相似文献
9.
A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I g-V g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I g- V g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I g-V g measurements 相似文献
10.
Hot carrier degradation of p-MOS devices at low gate voltages (V g<V d) is examined. It is shown that the electronic gate current is the principal factor in stress damage in this gate voltage range and that the damage itself consists of trapped electrons, localized close to the drain junction. The saturation of the transconductance change as a function of time which is seen at long stress times of high stress voltages results from a change in the injected gate current as a function of time. This is caused by changes in electric field in the silicon due to charge trapping in the oxide during stress. The saturation effect can, however, be transformed into a simple power law if the time axis is multiplied by the square of the instantaneous gate current. This allows for the development of a lifetime-prediction method. The method is applied to 1.0-μm p-MOS devices, and a lifetime is estimated 相似文献
11.
Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V d =8 V and V g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V b), having a power-law gradient of 0.5 for V b=0 V and 0.3 for V b=-9 V. Investigation of the type of damage resulting from stressing shows that at V b=0 V, interface state generation results, while at V b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions 相似文献
12.
Oxide charge buildup during channel-hot-carrier (CHC) injection was investigated by the use of a modified charge-pumping technique. An apparent `turnaround' effect in local oxide charge density during low gate voltage (V T<V g<1/2 V d) stressing was observed. It can be explained by the dynamic evolution of the damage location caused by the continuous changes in the electric field distribution during CHC. Dependence on channel length is also presented 相似文献
13.
Marchetaux J.-C. Bourcerie M. Boudou A. Vuillaume D. 《Electron Device Letters, IEEE》1990,11(9):406-408
The evolution of the gate current-voltage (I g- V gs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (V ds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the I g-V gs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is representative of the V gs=V ds case. It is demonstrated that electron traps are created in the oxide by both hot-hole and hot-electron injection stresses. They are not present in the devices before aging. They can be easily charged and discharged by short electron and hole injections, respectively 相似文献
14.
Electron trap creation under conditions of hot-electron stress (i.e., stress at V d=V g) is examined. It is shown that a relationship exists linking lifetime to the injected gate current and drain current, offering a lifetime prediction method for these types of traps. Comparing this type of damage to interface trap (N it) creation, it is found that larger energies (approximately 1.5 times that for N it) are required to generate this defect. It is shown that an extrapolation technique can be used to obtain gate currents at working circuit voltages, extending the prediction of lifetimes for oxide trap creation to low voltages 相似文献
15.
The performance of n-MOSFETs with furnace N2O-annealed gate oxides under dynamic Fowler-Nordheim bipolar stress was studied and compared with that of conventional oxide (OX). Time-dependent dielectric breakdown at high frequency was shown to be improved for the N2 O-annealed devices compared with that for devices with OX. In addition, a smaller V t shift after stress was found for nitrided samples. The shift decreased with increasing stressing frequency and annealing temperature. Measurements of both G m and D it revealed a peak frequency at which the degradation was the worst. A hole trapping/migration model has been proposed to explain this 相似文献
16.
Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In0.52 Al0.48As/In0.53Ga0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V G=0 V, the carrier density n g under the gate is 9×1011 cm-2, while outside of the gate region n g=2.1×1012 cm-2. The mobility under the gate at 4.2 K is as low as 400 cm2/V-s when V G<0.1 V and rapidly approaches 11000 cm2/V-s when V G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V G>0.1 V 相似文献
17.
Feuer M.D. Tennant D.M. Kuo J.M. Shunk S.C. Tell B. Chang T.-Y. 《Electron Device Letters, IEEE》1989,10(2):70-72
In0.52Al0.48As/In0.53Ga0.47 As/InP heterostructure insulated-gate field-effect transistors (HIGFETs) with gate lengths from 1.1 and 0.3 μm have been fabricated, and their electrical performance is characterized at DC and microwave frequencies. The refractory-gate self-aligned process, applied to devices with In0.53Ga0.47As channels, yields an unprecedented combination of very-high speed and excellent uniformity. HIGFETs with L g=0.6 μm showed average peak transconductance g m of 528 mS/mm and unity-current-gain cutoff frequency f t of 50 GHz. The uniformity of g m was better than 1%, and the voltage of the gm peak was uniform to ±30 mV. HIGFETs with L g=0.3 μm showed f 1 up to 63 GHz, but suffered from serious short-channel effect, due to excessive thickness of the InGaAs channel layer. A self-aligned technique for gate resistance reduction is shown to substantially improve microwave power gain 相似文献
18.
An In0.41Al0.59As/n+-In0.65 Ga0.35As HFET on InP was designed and fabricated, using the following methodology to enhance device breakdown: a quantum-well channel to introduce electron quantization and increase the effective channel bandgap, a strained In0.41Al0.59As insulator, and the elimination of parasitic mesa-sidewall gate leakage. The In0.65Ga0.35As channel is optimally doped to N D=6×1018 cm-3. The resulting device (L g=1.9 μm, W g =200 μm) has f t=14.9 GHz, f max in the range of 85 to 101 GHz, MSG=17.6 dB at 12 GHz V B=12.8 V, and I D(max)=302 mA/mm. This structure offers the promise of high-voltage applications at high frequencies on InP 相似文献
19.
Dependence of ionization current on gate bias in GaAs MESFETs 总被引:1,自引:0,他引:1
Canali C. Neviani A. Tedesco C. Zanoni E. Centronio A. Lanzieri C. 《Electron Devices, IEEE Transactions on》1993,40(3):498-501
The nonmonotonic behavior of gate current I g as a function of gate-to-source voltage V gs is reported for depletion-mode double-implant GaAs MESFETs. Experiments and numerical simulations show that the main contribution to I g (in the range of drain biases studied) comes from impact-ionization-generated holes collected at the gate electrode, and that the bell shape of the I g(V gs) curve is strongly related to the drop of the electric field in the channel of the device as V gs is moved towards positive values 相似文献
20.
Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N2O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N2O oxide has significant improvement in t BD (2×under-V g unipolar stress, 20×under+V g unipolar stress, and 10×under bipolar stress). The improvement of t BD in N2O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO2/Si interface 相似文献