High-Q factor three-dimensional inductors

In this paper, the great flexibility of three-dimensional (3-D) monolithic-microwave integrated-circuit technology is used to improve the performance of on-chip inductors. A novel topology for high-Q factor spiral inductor that can be implemented in a single or multilevel configuration is proposed. Several inductors were fabricated on either silicon substrate (/spl rho/ = 30 /spl Omega/ /spl middot/ cm) or semi-insulating gallium-arsenide substrate demonstrating, more particularly, for GaAs technology, the interest of the multilevel configuration. A 1.38-nH double-level 3-D inductor formed on an Si substrate exhibits a very high peak Q factor of 52.8 at 13.6 GHz and a self-resonant frequency as high as 24.7 GHz. Our 4.9-nH double-level GaAs 3-D inductor achieves a peak Q factor of 35.9 at 4.7 GHz and a self-resonant frequency of 8 GHz. For each technology, the performance limits of the proposed inductors in terms of quality factor are discussed. Guidelines for the optimum design of 3-D inductors are provided for Si and GaAs technologies.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

High-performance large-inductance embedded inductors in thin array plastic packaging (TAPP) for RF system-in-package applications

We report the first demonstration of high-Q embedded inductors fabricated using a thin-array-plastic-packaging (TAPP) technology. The TAPP technology provides a platform that integrates digital, analog, RF integrated circuits, along with high-performance passive components for system-in-package implementation. Embedded inductors ranging from 14 to 300 nH were fabricated. All the inductors with inductance less than 100 nH exhibit self-resonant frequency above 1 GHz. For a 14-nH inductor, Q factor of 35 was achieved at 1.6 GHz and the self-resonance frequency was measured at 6.15 GHz.     

Impedance Measurements of Microwave Lumped Elements from 1 to 12 GHz

The impedance measurement of small, microwave lumped elements of the order of 1 mm has been extended up to 12 GHz by a technique in which the frequency and Q of a resonant transmission line are perturbed by the connection of a lumped element. With the use of low-loss resonant coaxial lines, the technique has been applied to the measurement of lumped-element capacitors ranging from 0.4 to 3.6 pF and inductors ranging from 1.1 to 4.3 nH. Conductor Q values for capacitors as high as 1700 at 1.4 GHz and 100 at 12 GHz have been measured and estimates of dielectric Q values for capacitors of over 5000 have been obtained. Single-turn 1.1-nH inductor Q's of 40 at 1 GHz and 90 at 7 GHz have also been measured. The capacitors and single-turn inductors are found to have constant C and L values up to 12 GHz.     

Micromachined high-Q inductors in a 0.18-μm copper interconnectlow-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-μm digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 μm     

A simple systematic spiral inductor design with perfected Q improvement for CMOS RFIC application

In this paper, a systematic design procedure based on key factor analysis of the Q curve has been proposed. In addition to inductor design, we also present a technique that combines optimized shielding poly, and proton implantation treatment is utilized to improve the inductor Q value. The shielding effect of poly-silicon and the semi-insulating characteristics of proton-bombarded substrate have added a 37% and 54% increment to the Q value of the inductors, respectively. The combination of the two means has created a multiplication of their individual contribution rather than addition. The dramatic improvement of the Q value resulted from the doping level and film thickness optimization of a poly shield layer combined with a proton implantation treatment. A phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. This technique shall become a critical measure to put inductors on a silicon substrate with satisfactory performance for Si-based RF integrated-circuit applications     

Q-factor definition and evaluation for spiral inductors fabricated using wafer-level CSP technology

A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for inductors, a short-circuited load condition is used, where the Q factor is represented by using Y-parameters as Q=Im{1/Y/sub 11/}/Re{1/Y/sub 11/}. This conventional method provides a Q factor of 20 with 2-5-nH inductance around 3.9 GHz. However, since structures for the spiral inductors are asymmetrical, the short-circuited load condition and short-circuited source condition give different Q values, respectively. The Q-value differences of approximately 100% have often been observed in the WLP. The differences mainly come from differences in loss estimation. In a novel method, a complex conjugate impedance-matching condition is retained both at an input port and an output port of the inductor. The maximum available power gain (G/sub AMAX/) is introduced to evaluate the energy loss in one cycle. This condition provides a unique insertion loss of passive devices. Thus, the difference of the Q factor depends only on the difference of magnetic and electric energy. The difference of the Q value is reduced.     

An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

金属线宽及线间距渐变的射频螺旋电感

为减少射频螺旋电感的金属导体损耗,提出了一种电感金属线宽及金属间距从外到内逐渐变小的新颖结构.与传统的固定金属线宽和间距的电感相比,该渐变结构电感涡流效应的影响较小,金属导体损耗减小,从而降低其串联电阻,品质因子Q值提高.实验结果确证了所提方法的正确性.对一个高阻硅衬底上6nH电感,优化设计的渐变结构电感Q值在2.46GHz处可达到14.25,比版图面积相同、固定线宽及间距的传统电感高11.3%.因此,在无线通信系统的射频前端,采用这种电感与射频集成电路结合,能获得更好的射频电路性能.     

Performance Analysis of RF Spiral Inductor with Gradually Changed Metal Width and Space

To decrease the metal losses of RF spiral inductor,a novel layout structure with gradually reduced metal line width and space from outside to inside is presented.This gradual changed inductor has less eddy-current effect than the conventional inductor of fixed metal width and space.So the series resistance can be reduced and the quality (Q) factor of the inductor relating to metal losses is increased.The obtained experimental results corroborate the validity of the proposed method.For a 6nH inductor on high-resistivity silicon at 2.46GHz,Q factor of 14.25 is 11.3% higher than the conventional inductor with the same layout size.This inductor can be integrated with radio frequency integrated circuits to gain better performance in RF front end of a wireless communication system.     

High Q multilayer spiral inductor on silicon chip for 5/spl sim/6 GHz

High Q-values of spiral inductors at frequency around 5/spl sim/6 GHz have been achieved with a multilayer spiral (MLS) structure on a high loss silicon substrate. Compared to a one-layer spiral (OLS) inductor, the Q-value of a 4-nH inductor has been improved by about 80% at 5.65 GHz. The impact of the structure on Q-value and resonant frequency has been analyzed, which shows that an optimal height for the via of MLS inductors should be considered when inductors are designed. The fabrication process is compatible with Cu/SiO/sub 2/ interconnect technology.     

Micromachined microwave planar spiral inductors and transformers

A new micromachined planar spiral inductor, with the strips suspended individually, has been fabricated in standard GaAs high electron-mobility transistor monolithic-microwave integrated-circuit technology through maskless front-side bulk micromachining. The electronic compatibility, the use of industrial integrated-circuit production lines, the straightforward and low-cost additional procedure for structure releasing, and the very short etching time required are the principal features related to such a novel inductor structure. Moreover, the air-gap layer created underneath the device and between the strips significantly reduces shunt and fringing parasitic capacitances, consequently increasing the performance and operating frequency range. Experimental measurements, carried out up to 15 GHz, before and after micromachining, showed for a 12-nH inductor an increase of the maximum Q factor from 5 (at 3 GHz) to about 20 (at 7 GHz), while the self-resonant frequency was shifted from 5 to 13 GHz. Furthermore, a structure with two interleaved spiral inductors, in a 1:1 transformer-like configuration, was also fabricated, and its performance verified in order to demonstrate the promising performance improvements provided by the proposed device. Finally, heating and mechanical characteristics associated with freestanding microstructures are briefly evaluated using finite-element method simulations     

非均匀金属线宽和线间距射频螺旋电感品质因子的改善

为了提高品质因子Q,本文提出了一种非均匀金属条宽和非均匀条间距的改进电感结构。从外圈到里圈,改进的电感金属线宽按等差数列逐渐减小,金属间距按等比数列增加。因为该渐变结构有效减弱了线圈中心电流拥挤导致的涡流效应,所以改进结构电感的Q因子大幅度提高（幅值高达42.86%）。为了进一步增大Q因子,新型电感同时采用图形化接地保护结构（PGS）与渐变结构。结果显示,在0.5GHz到16GHz的射频频段内,结合两种技术的新型电感的品质因子Q最优,与固定金属线宽和间距的传统电感相比,Q提高了67%;与仅采纳PGS结构的电感相比,Q提高了23%;与仅采用渐变金属结构的电感相比,Q提高了20%。     

Balancing temperature dependence of on-wafer SOS inductors

The inductance and the quality factor (Q) of on-wafer inductors have a strong temperature dependence. For balancing unwanted temperature-induced variation, two different layout structures for silicon-on-sapphire (SOS) inductors were studied. One test series used metal inductors with a varying number of vias and the other metal inductors with silicon-based coils added. The tested silicon coil materials were polysilicon and n-diffusion and p-diffusion silicon. At the temperature of 423 K, the metal inductor with the highest number of vias gave less decreased Q. A silicon coil increases the parasitic capacitance of the inductor, which decreases the self-resonant frequency. Thus, the Q of the inductor with the polysilicon coil was equal to or better than that of the plain metal inductor up to the frequency of 8 GHz. Furthermore, the polysilicon coil balanced the temperature dependent variations reflected to the inductance and the self-resonant frequency. The inductor with the polysilicon coil had the best and the most stable characteristics in the measured temperature range, from 233 K to 423 K. The present results are important for the design of System-in-Package (SiP) stacked systems in which local power densities may be increased.     

一种采用LC谐振电路的高频差分有源电感

提出了一种采用LC并联谐振电路的新型差分有源电感,实现了宽的工作频带、高的Q值、较大的电感值和可调谐功能.采用无源电感和MOS晶体管可变电容构成LC谐振电路,减小了等效串联电阻和等效并联电容,在增大电感值、Q值的同时,扩大了工作频带.仿真结果表明,在2～7.6 GHz频率范围内,该新型差分有源电感的电感值大于26 nH...     

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.     

On-chip solenoid inductors with high quality factor for high frequency magnetic integrated circuits

On-chip solenoid inductors for high frequency magnetic integrated circuits are proposed. The eddy current loss was reduced by dividing the inductor into three consecutive inductors connected in series. The inductor has an inductance of 1.1nH and the maximum quality factor (Q/sub max/) of 50.5. The self-resonant frequency and the operating frequency at Q/sub max/ are greater than 17.5GHz and 16.7GHz, respectively.     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.