宽带隙ZnMgO的电学特性及其透明薄膜场效应晶体管

首次提出了用六方相晶体结构的宽带隙ZnMgO作为薄膜场效应晶体管(TFT)的沟道层,用立方相ZnMgO纳米晶体薄膜作为栅绝缘层,在实验中用透明的ITO导电玻璃作为衬底,通过连续沉积六方和立方相结构的纳米ZnMgO晶体薄膜,并通过光刻、电极工艺等,研制了透明的ZnO基TFT,TFT的电流开关比达到104,场效应迁移率为0.6cm2/(V·s).在偏压2.5MV/cm下漏电流为10-8A.     

宽带隙ZnMgO的电学特性及其透明薄膜场效应晶体管

首次提出了用六方相晶体结构的宽带隙ZnMgO作为薄膜场效应晶体管(TFT)的沟道层,用立方相ZnMgO纳米晶体薄膜作为栅绝缘层,在实验中用透明的ITO导电玻璃作为衬底,通过连续沉积六方和立方相结构的纳米ZnMgO晶体薄膜,并通过光刻、电极工艺等,研制了透明的ZnO基TFT,TFT的电流开关比达到104,场效应迁移率为0.6cm2/(V·s).在偏压2.5MV/cm下漏电流为10-8A.     

ZnTe∶Cu薄膜的制备及其性能

用共蒸发法在室温下沉积了ZnTe∶Cu多晶薄膜.刚沉积的不掺Cu的薄膜呈立方相，适度掺Cu时为立方相和六方相的混合相.随着Cu含量的增加，六方相增加，光能隙减小.根据暗电导温度关系，结合XRD和DSC的结果，认为在110℃、170℃开始出现类CuTe、类Cu2Te相以及Cu0、Cu＋离解的结果导致电导温度关系异常，应用这种薄膜作为背接触层获得了转换效率为11.6%，面积为0.52cm2的CdS/CdTe/ZnTe∶Cu太阳电池.     

立方ZnMgO基体中六方ZnO量子点的化学溶液制备技术

首次报道了利用相分凝技术在非晶石英衬底上立方ZnMgO基体中制备六方ZnO量子点的化学溶液方法.对所制备的ZnO/ZnMgO/SiO2进行了原子力显微镜(AFM)、X射线衍射(XRD)、光致发光(PL)、椭圆偏振光谱(SE)表征.XRD表征表明当六配位Zn2 以替位的形式取代六配位Mg2 时,会导致相同衍射条件下立方ZnMgO的2θ比立方MgO的2θ小.SE表征发现ZnO量子点的量子效应导致了ZnO量子点的激子吸收能(3.76eV)比ZnO体晶的能带隙(3.37 eV)大.AFM表征表明:导致薄膜的XRD的衍射峰、α吸收峰和PL发射峰皆很宽的部分原因是由于组成所制备薄膜的晶粒尺寸分散较大、形状不一引起的.     

直流反应磁控溅射Zn1-xCdxO薄膜的研究

用直流反应磁控溅射法在n-Si(111)和玻璃衬底上生长高度择优取向的Zn1-xCdxO合金晶体薄膜,最佳生长温度为450℃(x＝0.2).当x≤0.6时,Zn1-xCdxO薄膜具有纯ZnO的六角结构,x＝0.8时,薄膜是由ZnO六角结构晶体和CdO立方结构晶体组成的混合物.透射光谱测试表明,通过改变合金薄膜中Cd的含量,可以调节Zn1-x-CdxO薄膜的禁带宽度.     

直流反应磁控溅射Zn_(1-x)Cd)_xO薄膜的研究

用直流反应磁控溅射法在n Si(111)和玻璃衬底上生长高度择优取向的Zn1-xCdxO合金晶体薄膜,最佳生长温度为45 0℃(x=0 2 ) .当x≤0 6时,Zn1-xCdxO薄膜具有纯ZnO的六角结构,x =0 8时,薄膜是由ZnO六角结构晶体和CdO立方结构晶体组成的混合物.透射光谱测试表明,通过改变合金薄膜中Cd的含量,可以调节Zn1-x CdxO薄膜的禁带宽度.     

立方GaAs（100）衬底上制备单相六方GaN薄膜

立方GaAs（100）衬底上制备的GaN薄膜多为立方结构且立方相为亚稳相,采用水平常压MOCVD方法在立方GaAs（100）衬底上制备出了GaN薄膜．XRD测试表明,薄膜具有单一的相．结合对工艺条件的分析,认为薄膜具有六方结构．最后,通过Raman光谱测试,证实在立方GaAs衬底上制备出了单相六方GaN薄膜．还对立方GaAs衬底上制备出六方GaN薄膜的原因进行了讨论．     

化学水浴沉积CdS薄膜晶相结构及性质

采用CBD法在醋酸镉溶液体系中制备CdS半导体薄膜，研究了溶液组份的浓度对CdS结晶结构的影响．增加乙酸胺的浓度、提高溶液的pH值有利于生成立方晶CdS，反之则易于生成六方晶CdS．无论立方相还是六方相CdS薄膜，电阻率均在10~4～10~5Ω·cm范围，结晶均匀细致．用六方晶为主和立方晶为主的CdS制备的CIGS太阳电池最高效率分别达到12.10%和12.17%．     

ZnTe Cu薄膜的制备及其性能

用共蒸发法在室温下沉积了 Zn Te∶ Cu多晶薄膜 .刚沉积的不掺 Cu的薄膜呈立方相 ,适度掺 Cu时为立方相和六方相的混合相 .随着 Cu含量的增加 ,六方相增加 ,光能隙减小 .根据暗电导温度关系 ,结合 XRD和 DSC的结果 ,认为在 110℃、170℃开始出现类 Cu Te、类 Cu2 Te相以及 Cu0、Cu+离解的结果导致电导温度关系异常 ,应用这种薄膜作为背接触层获得了转换效率为 11.6 % ,面积为 0 .5 2 cm2 的 Cd S/Cd Te/Zn Te∶ Cu太阳电池     

ZnTeCu薄膜的制备及其性能

用共蒸发法在室温下沉积了 Zn Te∶ Cu多晶薄膜 .刚沉积的不掺 Cu的薄膜呈立方相 ,适度掺 Cu时为立方相和六方相的混合相 .随着 Cu含量的增加 ,六方相增加 ,光能隙减小 .根据暗电导温度关系 ,结合 XRD和 DSC的结果 ,认为在 110℃、170℃开始出现类 Cu Te、类 Cu2 Te相以及 Cu0、Cu+离解的结果导致电导温度关系异常 ,应用这种薄膜作为背接触层获得了转换效率为 11.6 % ,面积为 0 .5 2 cm2 的 Cd S/Cd Te/Zn Te∶ Cu太阳电池     

用超声喷雾热分解法制备p型Zn1-xMgxO薄膜

利用超声喷雾热分解(USP)技术,采用N-Al共掺法,在eagle2000衬底上制备出了电学特性较好的p型Zn0.93Mg0.07O薄膜:电阻率为18.43Ω.cm、迁移率是0.362 cm2/(V.s)、载流子浓度为1.24×1018cm-3。系统分析了前驱溶液中Al掺杂量或Mg掺杂量变化时对p型Zn1-xMgxO薄膜电学特性和结构特性的影响。紫外可见光透射测试表明:Zn1-xMgxO薄膜在紫外-可见光范围内的透过率达到了80%。     

The Influence of Channel Compositions on the Electrical Properties of Solution-Processed Indium-Zinc Oxide Thin-Film Transistors

Electrical properties of indium-zinc oxide (IZO) thin-film-transistors (TFTs) based on solution processes with various channel compositions are investigated in this paper. Amorphous IZO thin films with high transparency and smooth/uniform surfaces are deposited by spin-coating. The In:Zn ratio is varied by adjusting the precursor compositions, and its influences on the electrical properties, such as resistivity, mobility, and threshold voltage, etc., of IZO films and TFTs are studied. The devices showed field effect mobility ranging from 0.07 to 2.13 ${hbox{cm}}^{2}/{hbox{V}}cdot{hbox{s}}$ with the In component $({hbox{In}}/({hbox{In}}+{hbox{Zn}}))$ varying from 0.2 to 0.5.      

脉冲激光沉积法制备ZnO基薄膜研究进展

作为一种新型的Ⅱ-Ⅵ半导体材料,ZnO具有优良的光学和电学性能,在紫外光发射器件、自旋功能器件、气体探测器、表面声波器件等领域有着广阔的应用前景.首先介绍了ZnO材料和脉冲激光溅射法的一些相关内容,然后从材料制备角度着重阐述了目前利用脉冲激光沉积法(PLD)制备ZnO基薄膜的若干重要研究方向,例如p型掺杂、p-n结的制备、Mg掺杂、Cd掺杂和磁性离子掺杂等.     

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.     

Dependence of single-crystalline Si TFT characteristics on the channel position inside a location-controlled grain

To obtain high-performance thin-film transistors (TFTs), a comprehensive study of the channel position of TFTs inside a location-controlled grain was carried out. The location of the grain is precisely controlled by the /spl mu/-Czochralski process using an excimer laser. The grain was grown from a thin Si column embedded in SiO/sub 2/ (grain filter). The characteristics of the TFTs drastically improved when the channel region was not centered above the grain filter. With TFTs whose current-flow direction is parallel to the radial direction of the grain filter, an electron mobility and subthreshold swing of /spl sim/600cm/sup 2//V/spl middot/s and 0.21V/dec respectively were obtained.     

Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric

This investigation is the first to demonstrate a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si (LTPS) thin film transistors (TFTs), composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O-plasma. The stack oxide shows a very high electrical breakdown field of 8.4 MV/cm, which is approximately 3 MV/cm larger than traditional PECVD TEOS oxide. The field effective mobility of stack oxide LTPS TFTs is over 4 times than that of traditional TEOS oxide LTPS TFTs. These improvements are attributed to the high quality N/sub 2/O-plasma grown ultrathin oxynitride forming strong Si/spl equiv/N bonds, as well as to reduce the trap density in the oxynitride/poly-Si interface.     

The effects of electrical stress and temperature on the propertiesof polycrystalline silicon thin-film transistors fabricated by metalinduced lateral crystallization

An asymmetric Ni-offset method was proposed to improve the electrical properties of poly-Si thin-film transistors (TFTs) fabricated by metal-induced lateral crystallization (MILC). The MILC/MILC boundary, which was inevitably located within the channel when formed by symmetric Ni-offset, could be successfully extracted from channel region by new asymmetric Ni-offset method. Therefore, thus fabricated TFTs showed lower leakage current and better thermal stability than symmetric Ni-offset TFTs. In addition, the effects of electrical stress and temperature on the electrical properties of symmetric/asymmetric Ni-offset TFTs were investigated     

Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.     

A high-performance multichannel dual-gate poly-Si TFT fabricated by excimer laser irradiation on a floating a-Si thin film

A new excimer laser annealing (ELA) process that uses a floating amorphous-Silicon (a-Si) thin film with a multichannel structure is proposed for high-performance poly-Si thin-film transistors (TFTs). The proposed ELA method produces two-dimensional (2-D) grain growth, which can result in a high-quality grain structure. The dual-gate structure was employed to eliminate the grain boundaries perpendicular to the current flow in the channel. A multichannel structure was adapted in order to arrange the grain boundary to be parallel to the current flow. The proposed poly-Si TFT exhibits high-performance electrical characteristics, which are a high mobility of 504 cm/sup 2//Vsec and a low subthreshold slope of 0.337 V/dec.     

Skin‐Like Oxide Thin‐Film Transistors for Transparent Displays

Flexible transparent display is a promising candidate to visually communicate with each other in the future Internet of Things era. The flexible oxide thin‐film transistors (TFTs) have attracted attention as a component for transparent display by its high performance and high transparency. The critical issue of flexible oxide TFTs for practical display applications, however, is the realization on transparent and flexible substrate without any damage and characteristic degradation. Here, the ultrathin, flexible, and transparent oxide TFTs for skin‐like displays are demonstrated on an ultrathin flexible substrate using an inorganic‐based laser liftoff process. In this way, skin‐like ultrathin oxide TFTs are conformally attached onto various fabrics and human skin surface without any structural damage. Ultrathin flexible transparent oxide TFTs show high optical transparency of 83% and mobility of 40 cm² V^?1 s^?1. The skin‐like oxide TFTs show reliable performance under the electrical/optical stress tests and mechanical bending tests due to advanced device materials and systematic mechanical designs. Moreover, skin‐like oxide logic inverter circuits composed of n‐channel metal oxide semiconductor TFTs on ultrathin, transparent polyethylene terephthalate film have been realized.