Pt/Si界面化学键性质的研究

在超高真空系统中,超薄层 Pt淀积膜原位蒸发在原子清洁的 Si(111)表面上形成 Pt/Si界面.利用光电子谱技术(XPS和UPS)研究了Pt/Si 界面的化学性质.测量了Si2p和Pt 4f芯能级和价带电子态,并着重研究这些芯能级及电子态在低覆盖度时的变化.由 Si(2p)峰的强度随 Pt 覆盖度的变化可以清楚证明:在 300 K下淀积亚单原子层至数个单原子层 Pt的 Pt/Si(111)界面发生强烈混合作用,其原子组伤是缓变的.由于Si原子周围的 Pt原子数不断增加,所以 Pt 4f芯能级化学位移随 Pt原子覆盖度的增加而逐步减小,而Si 2p芯能级化学位移则逐步增大.同时,Pt 4f峰的线形也产生明显变化,对称性增加;Si 2p峰的线形则对称性降低.淀积亚单原子层至数单原子层Pt的UPS谱,主要显示两个峰:-4.2eV(A峰),-6.0eV(B峰).A峰随着覆盖度的增加移向费米能边,而B峰则保持不变.这说明Ptd-Sip键合不受周围Pt原子增加的影响.利用Pt/Si界面Pt原子向Si原子的间隙扩散模型讨论了所观察到的结果.     

CeO_2高K栅介质薄膜的制备工艺及其电学性质

研究了 Ce O2 作为高 K (高介电常数 )栅介质薄膜的制备工艺 ,深入分析了衬底温度、淀积速率、氧分压等工艺条件和利用 N离子轰击氮化 Si衬底表面工艺对 Ce O2 薄膜的生长及其与 Si界面结构特征的影响 ,利用脉冲激光淀积方法在 Si(10 0 )衬底生长了具有 (10 0 )和 (111)取向的 Ce O2 外延薄膜 ;研究了 N离子轰击氮化 Si衬底表面处理工艺对 Pt/ Ce O2 / Si结构电学性质的影响 .研究结果显示 ,利用 N离子轰击氮化 Si表面 /界面工艺不仅影响 Ce O2 薄膜的生长结构 ,还可以改善 Ce O2 与 Si界面的电学性质     

CeO2高K栅介质薄膜的制备工艺及其电学性质

研究了CeO2作为高K(高介电常数)栅介质薄膜的制备工艺,深入分析了衬底温度、淀积速率、氧分压等工艺条件和利用N离子轰击氮化Si衬底表面工艺对CeO2薄膜的生长及其与Si界面结构特征的影响,利用脉冲激光淀积方法在Si(100)衬底生长了具有(100)和(111)取向的CeO2外延薄膜;研究了N离子轰击氮化Si衬底表面处理工艺对Pt/CeO2/Si结构电学性质的影响.研究结果显示,利用N离子轰击氮化Si表面/界面工艺不仅影响CeO2薄膜的生长结构,还可以改善CeO2与Si界面的电学性质.     

Co/Ti/Si三元固相反应形成自对准TiN/CoSi_2复合薄膜

采用离子束溅射技术在Si片上先后连续淀积Ti膜和Co膜,对Co/Ti/Si三元体系固相反应特性进行了研究。在氮气氛下对Co/Ti/Si样品进行热处理,结果表明,样品薄层电阻及薄膜结构随热处理温度的升高发生显著变化。原来处于样品表面的Co穿过Ti膜与Si发生反应在薄膜内部形成钴硅化合物,在薄膜表面Ti与气氛中的N结合形成TiN。实验在有SiO_2图形的Si片上溅射Co/Ti,通过两步退火和选择腐蚀可在硅区域表面获得线条整齐的自对准TiN/CoSi_2复合薄膜。     

CeO2高K栅介质薄膜的制备工艺及其电学性质

研究了CeO2作为高K（高介电常数）栅介质薄膜的制备工艺,深入分析了衬底温度,淀积速率,氧化压等工艺条件和利用N离子轰击氧化Si衬底表面工艺对CeO2薄膜的生长及其与Si界面结构特征的影响,利用脉冲激光淀积方法在Si(100)衬底生成了具有（100）和（111）取向的CeO2外延薄膜,研究了N离子轰击氮化Si衬底表面处理工艺对Pt/CeO2/Si结构电学性质的影响,研究结果显示,利用N离子轰击氮化Si表面／界面工艺不仅影响CeO2薄膜的生长结构,还可以改善CeO2与Si界面的电学性质。     

Pt/Ti/Si三元固相反应生长PtSi过程的实验研究

采用离子溅射方法在硅衬底上淀积Pt/Ti/Si多层结构,研究了不同退火温度(500℃和800℃)、相同退火时间(30 min)固相反应形成PtSi薄膜的工艺.通过XRD、AES等测试方法,研究了原子的互扩散和反应过程.结果表明,在500℃退火时,由于Pt-Ti-O-Si过渡层的存在,使得Pt和Si反应不够充分,生成物中有部分Pt2Si存在,而800℃退火时,由于过渡层Ti与Si反应生成TiSi2,消耗了大量的Si,使得Pt与Si反应也不够充分.根据上述实验,给出了Pt/Ti/Si三元固相反应在不同退火温度下应采取的工艺务件.     

Ti/Si和Ti/SiO_2/Si系统硅化物的形成

用AES、XPS、RBS和X射线衍射等技术研究了在稳态热退火和激光退火条件下,Ti/Si和 Ti/SiO_2/Si系统硅化物的形成.在 500—600℃稳态热退火条件下,Ti/Si系统形成 Ti_5Si_3、TiSi和 TiSi_2三种硅化物;高于 650℃,只存在TiSi_2.TiSi_2的生长服从 △x∝t~(1/2).Ti/SiO_2/Si系统,750℃以上退火,形成覆盖层为TiO 的Ti_5Si_3薄膜,△x∝t~(1/2). CW-Ar~+激火扫描退火Ti/Si样品,功率密度小于2.7kW/cm~2,产生固相反应;功率密度～3.8kW/cm~2,产生液相反应,并形成TiSi_2和纯Si的混合薄膜.对实验结果进行了讨论.     

NiSi/Si界面的剖面透射电镜研究

采用不同硅化工艺制备了NiSi薄膜并用剖面透射电镜(XTEM)对样品的NiSi/Si界面进行了研究.在未掺杂和掺杂(包括As和B)的硅衬底上通过物理溅射淀积Ni薄膜,经快速热处理过程(RTP)完成硅化反应.X射线衍射和喇曼散射谱分析表明在各种样品中都形成了NiSi.还研究了硅衬底掺杂和退火过程对NiSi/Si界面的影响.研究表明:使用一步RTP形成NiSi的硅化工艺,在未掺杂和掺As的硅衬底上,NiSi/Si界面较粗糙;而使用两步RTP形成NiSi所对应的NiSi/Si界面要比一步RTP的平坦得多.高分辨率XTEM分析表明,在所有样品中都形成了沿衬底硅〈111〉方向的轴延-NiSi薄膜中的一些特定晶面与衬底硅中的(111)面对准生长.同时讨论了轴延中的晶面失配问题.     

Ti扩散势垒对Al／Si／Pd与n—GaAs欧姆接触热稳定性的影响

利用电子束蒸发依次将Pd,Si和Al淀积在掺杂浓度为2×10~(13)cm~(-3)的n型GaAs上,可以得到非合金、低阻的欧姆接触。比接触电阻率约为5×10~(-6)·cm~2。但经过高温(410℃),长时间热退火后,样品的表面会出现明显不平整,比接触电阻率会明显增加,在Al和Si/Pd之间加入一层Ti作为扩散势垒会使欧姆接触的热稳定性变好。但只有在Al和Ti之间的反应没有完全耗尽Ti时,扩散势垒才起作用。     

磁控溅射生长Cu/Si薄膜

用溅射方法在Si(111)上生长Cu/Si,Ti/Si,Cu/Ti/Si薄膜。用XRD,红外吸收光谱,台阶仪对薄膜进行分析和测量。结果表明:在150℃溅射生长出的Cu/Ti/Si薄膜的缓冲层为硅化物TiSi2(311);Cu薄膜的主要成分是晶粒大小为17nm的Cu(111);Cu/Ti/Si(111)平均厚度为462nm,粗糙度为薄膜厚度的3%。在以TiSi2薄膜为缓冲层的Si(111)衬底上生长出的Cu薄膜抗氧化性较强、薄膜均匀性和致密性较好。     

Si/Ti/Au/Si键合技术研究及其应用

运用Si／Ti／Au／Au／Ti／Si在N2保护下及420℃左右，成功地实现了Au／Si共熔键合，成品率达到90％以上。该键合方法能进行选择区域键合，完全避免了由于Si／Si熔融键合过程中高温退火给微电子机械系统(MEMS)器件带来的畸变甚至失效，为新型室温红外探测器的研制奠定了良好的工艺基础，是此类结构MEMS器件的理想键合封装方法。     

Double-Junction Schottky Diodes Using a Ti/Si/Al Structure

Ti/Si/Al structures are studied theoretically and experimentally. The effect of the reverse-biased junction on the current–voltage characteristic of the entire structure is revealed. It is noted that the behavior of the curve is determined by the image-force lowering of the potential barrier. The current–voltage characteristic is shown to obey a power law if the voltage is low enough. It is established that the capacitance of the structure decreases with increasing voltage if the latter is positive. This phenomenon is modeled using two capacitors in a series.     

First stages of silicidation in Ti/Si thin films

The structural evolution in fiber-textured Ti/Si thin films was investigated by in-situ X-ray diffraction in the temperature range preceding the formation of silicide compounds. Abnormal thermal behaviour of both 002 and 101 diffraction profiles was observed at 360 and 450 °C, which could be understood in terms of Si diffusion, first in Ti grain boundaries, then into the grains. By combining ex-situ strain studies with analysis of the Si local environment in the whole Ti silicide family from Ti₅Si₃ to TiSi₂, it was possible to determine the stress-free lattice parameters of annealed films. They are significantly higher than the bulk parameters, and indicate that nearly 4.5 at.% Si is present in the Ti grains.     

Evolution of the Co–N/Ti/Si System in Magnetron Sputtering of Co onto a Heated Ti/Si(100) Substrate

The surface-diffusion interaction is studied experimentally between cobalt and a heated Ti/Si(100) substrate under reactive magnetron sputtering in an argon–nitrogen atmosphere. A model is proposed that accounts for the nature of silicide formation in the Co/Ti/Si system by volume and surface-diffusion reactions between cobalt and the substrate. It is shown that the diffusion of cobalt into the silicon is impeded by the TiSi _x layer to a far greater extent than by the Ti layer.     

二次退火对Al/Ti/n-GaN/Si欧姆接触的影响

采用热壁外延的方法在硅衬底上生长出n-GaN晶体,制成了Ti/Al双层电极的欧姆接触。通过对不同退火条件下的I-V特性曲线、X射线衍射及二次离子质谱分析,揭示了界面固相反应对该接触的影响,并提出了一种新的二次退火的方法。结果表明,经过二次退火后,Al、Ti、GaN发生了界面固相反应,其接触性能明显提高。     

Buckling and Delamination of Ti/Cu/Si Thin Film During Annealing

In this paper, the formation of buckling and delamination of sandwiched stacking of Ti/Cu/Si thin film are investigated. The crystallization structures, the composition of the Cu/Ti thin films, and the surface morphology are measured during annealing. The results show that the solid-phase reaction between Cu and Ti occurs at the interface. Buckling is initiated in the thin film annealed at 600°C. The volume expansion promotes the buckling and further produces microcracks. With increasing volume expansion, there are cavities formed in the middle layer when the annealing temperature is up to 700°C. Finally, thin film is delaminated from the substrate.     

Self-aligned Ti germanosilicide formation on a polycrystalline Si/SiGe/Si extrinsic base for SiGe heterojunction bipolar transistors

This work reports our investigation of a microstructure of self-aligned Ti germanosilicide made on polycrystalline Si/SiGe/Si multilayers. The existence of the SiGe layer restricted the growth of the Ti germanosilicide layer and produced protrusions penetrating the underlying polycrystalline layer. Each protrusion corresponded to a stacking-faulted single grain of the C49 phase. The microstructure of the thin Ti germanosilicide layer and the deep protrusions caused an increase of the sheet resistance and the contact resistivity of the extrinsic base region. The raised contact resistivity led to a degradation of radio frequency (RF) and noise characteristics of the SiGe heterojunction bipolar transistor (HBT).     

Auto-correlation function analysis of amorphous interlayers in Ti/Si systems

High-resolution transmission electron microscopy (HRTEM) in conjunction with auto-correlation function (ACF) analysis was utilized to determine the structure of the amorphous TiSi_x layer formed in the initial stage prior to the formation of crystalline silicides. Enhanced formation of C54-TiSi₂ on (0 0 1) Si by tensile stress and/or high-temperature sputtering was found. The present work strongly suggested that the presence of a high density of silicide crystallites in the amorphous TiSi_x layer leads to the favorable TiSi₂ formation.     

Manufacturing and materials properties of Ti/Cu/ElectrolessNi/solder bump on Si

This work attempted to fabricate the solder bump with the structure: Si/Ti/Cu/Electroless Ni/solder. The shear strength of the solder bump, with bump pad of 60 μm in diameter, is around 15 g/bump prior to and after reflow. The solder bumps fractured at the solder. Humidity test at 85% of relative humidity at 85°C and a high temperature treatment at 150°C for 1000 h tend to downgrade the shear strength of the solder portion of the bump, yet not the interface. Both treatments enhance the growth of intermetallic compound (IMC) formed between Ni and solder. The barrier effect of electroless nickel deposit was investigated