主动式雷达导引头三通道集成接收前端设计

介绍了一种主动式雷达导引头三通道集成接收前端的设计方案及技术要点,全文围绕小型化设计思想,详细阐述了各主要关键部件Ku波段单刀单掷开关、低噪声放大器、镜像抑制混频器及单通道接收机等电路设计及测试结果,并最终实现了多功能部件的系统集成,整个集成接收前端具有低噪声、高增益、高隔离度、高镜像抑制及集成度高的特点,在主动式雷达导引头前端系统中具有较好的应用前景。     

42GHz 波段接收机前端的设计与研制*

伴随着无线通信技术日新月异的发展,人们对宽频带、高速率、大容量通信系统的需求也日益增大.毫米波由于自身具有波长短、传输容量大等优点,日益受到研究人员的广泛关注和青睐.本文针对42GHz频段点对点高速通信应用,设计研制了该频段的毫米波接收机前端.该前端由三级低噪声放大器(LNA)、一级混频器和一个基片集成波导(siw)镜像抑制滤波器构成.射频(RF)信号工作在40.8GHz～ 42.8GHz频段内,中频(IF)固定在3.5GHz.测试结果显示,在工作频段内其变频增益大于15dB,射频输入功率ldB增益压缩点不低于-30dBm,接收机前端的噪声系数(NF)小于6dB.     

一款低噪声卫星导航接收机射频前端的设计

基于0.18tm RF CMOS工艺,采用低中频系统结构,设计了一款可应用于全球定位导航系统(GPS) L1频段和北斗二代(BD2) B1频段的低噪声卫星导航接收机的射频模拟前端芯片.该前端包括低噪声放大器、无源混频器、中频放大器、复数带通滤波器和数控可变增益放大器.其中低噪声放大器采用电流舵技术,与无源混频器一起,提高了射频前端的1 dB压缩点输入功率(Pi(1dB)),有效地改善了系统的线性度.测试结果显示,在GPS L1频点,系统的最大增益107.2 dB,噪声系数达到1.8 dB,动态增益66 dB,镜像抑制比约为39.54 dB,Pi(1dB)为-41 dBm,电源为1.8V时,消耗电流16 mA,芯片面积1.7 mm×0.8 mm.     

一种ISM 2.4GHz的低功耗低中频射频接收机前端

本文描述了一种工作在2.4GHz ISM频段的低功耗、低中频射频接收机前端电路,使用TSMC 0.13um CMOS工艺。整个前端包括一个低噪声放大器以及两次变频下变换混频器。低噪声放大器通过在输入级引入额外的栅-源电容实现了低功耗与低噪声的设计;在下变换混频器设计中,分别使用一个单平衡射频混频器以及两个双平衡低中频混频器实现两次变频下变换技术;射频混频器输入晶体管源极串联电感-电容谐振网络以及低噪声放大器输出级的电感-电容谐振网络总共实现了30dB的镜像抑制率。整个前端占用芯片面积约0.42mm2,在1.2V的供电电压下,仅耗功率4.5mW,实现了4dB的噪声系数,在高增益模式下,获得-22dBm的三阶交调线性度,整个链路电压增益为37dB。     

X波段微波低噪声混合集成接收前端

介绍了低噪声GaAsFET用作单脉冲跟踪雷达前端放大时的持点、系统构成以及低噪声放大器和镜像抑制混频器的设计方法和制作。测试结果性能满意，在近1GHZ频率范围内系统总噪声系数小于2．5dB，放大器增益大于20dB，混频器镜像抑制度大于20dB，三路放大器之间幅度不平衡小于0．8dB，相位不平衡小于7°。该混合集成微波前端已成功地用于某型火控雷达，对海面上低空小目标进行跟踪。     

K波段单片接收机设计

基于0.15μm GaAs PHEMT工艺,设计了一款K波段MMIC接收机,频率覆盖19～26 GHz。在单个芯片内集成了平衡式低噪声放大器、本振驱动放大器、镜像抑制次谐波混频器等电路。在19～26 GHz射频输入带宽内的转换增益为7 dB;噪声系数典型值为4 dB;输入回波损耗-12 dB;镜像抑制15 dB;本振-射频隔离度55 dB。为了降低了芯片成本,采用电磁场仿真软件对电路面积做优化设计,使得芯片面积仅为2 mm×4 mm。此接收机MMIC具有集成度高、可靠性高、体积小等特点,可广泛应用于各种微波通信系统和雷达系统。     

X波段低噪声放大器的设计与仿真

文中提出了一种X波段雷达接收机前端低噪声放大器的设计,该放大器选用性价比较高的伪形态高电子迁移率晶体管ATF36077,两级放大器电路分别按照最佳噪声系数和高增益的要求进行网络匹配设计。在设计过程中,引入噪声量度概念对总体电路的指标进行衡量,利用商业软件ADS进行电路的仿真与优化设计。仿真结果表明,该低噪声放大器在9310 MHz~9510 MHz 工作频段内,其噪声系数优于0.51 dB,增益大于20 dB,输出1 dB 压缩点为12.8 dBm。绘制版图,通过合理布局,整体结构紧凑,尺寸仅为42 mm×30 mm,可应用于X波段船舶导航雷达接收机前端中。     

Ku波段雷达接收机设计

阐述了Ku波段雷达接收机的工作原理进行了阐述,并对设计方案与测试结果进行了分析。Ku波段接收机由低噪声变频单元、中频放大、本振和电源4个独立单元组成。对各单元电路的设计进行了分析,给出了元器件选型以及仿真结果。试验结果表明,Ku波段接收机的噪声系数≤1.0 dB、增益≥55 dB、输入输出驻波,相位噪声杂散,镜像抑制等指标均满足实用技术要求,并根据测试结果对Ku波段接收机部分指标提出了进一步优化的方法。     

北斗导航接收机LNA的设计与仿真

为了实现北斗卫星导航接收机射频前端的研制,根据接收机射频模块系统指标要求,包括增益、噪声系数、灵敏度等关键指标要求,提出一种基于ATF54143的LNA设计方案,采用两级结构,源极传输线负反馈稳定技术,实现输入最佳噪声匹配,输出共轭匹配设计,并用ADS软件进行仿真,得到增益32dB,噪声系数0.45dB,输入驻波比1.5。     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A 5.25-GHz image rejection RF front-End Receiver With Polyphase filters

A 5.25-GHz image rejection (IR) radio frequency (RF) front-end receiver is proposed, which is implemented in 0.18-/spl mu/m CMOS technology. The proposed receiver adopts both a high-intermediate frequency (IF) and the double quadrature architecture to achieve high IR at 5-GHz frequency. The measured results show a power gain of 14 dB, a minimum noise figure of 7.9dB, and IIP3 of -8dBm. The measured maximum image rejection ratio is 45dBc. The receiver consumes a total of 32mA from a 1.8-V supply.     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

A 30 GHz MMIC receiver for satellite transponders

The development of 30-GHz-band monolithic microwave integrated circuits (MMICs) and multichip MMIC modules (low-noise amplifier and frequency converters) is reported. A 30-GHz-band full-MMIC receiver for satellite transponders was successfully constructed using the MMIC modules and the performance of the full-MMIC receiver is evaluated. Test results verify its successful performance as a satellite receiver system. The design and performance of the MMICs (a two-stage amplifier, an image rejection mixer, and a frequency multiplier), of multichip-type MMIC modules (a 30-GHz-band low-noise amplifier module with 30 dB gain and 8.2 dB noise figure, and an image rejection frequency converter with a 10 dB conversion loss and an 18 dB image rejection ratio) and of the full-MMIC receiver, which weighs 1/6 as much as a conventional hybrid integrated circuit are presented     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed.The relevant parameter analysis and the details of circuit design are presented.The test chip was implemented in a TSMC 0.18μm 1P4M RF CMOS process.The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz.The measured noise figure is around 1.5-1.7 dB on both bands.The LNA consumes less than 4.3 mA of current ...     

镜像频率抑制度对射频前端噪声系数的影响分析

探讨了镜频抑制度对于射频前端噪声系数的影响,分析计算了一次变频系统中有镜频抑制滤波器和无镜频抑制滤波器两种情况下射频前端输出的噪声功率值,分析表明镜频抑制滤波器在一次变频系统中能够改善系统噪声系数约3 dB;针对二次变频系统射频前端的输出噪声功率,分析计算表明当镜频抑制度达到20 dB 以上时,镜像频率对射频前端输出噪声的影响很小,近乎可以忽略。给出一种Ka频段二次变频射频前端的实例,测试结果与理论分析一致。     

GPS与北斗二代双频接收机低噪放模块设计实现

设计并实现了一款覆盖GPS L1波段和北斗二代B1波段的低噪放模块。该模块中的低噪声放大器使用分立元件搭建,匹配电路调试灵活,满足了模块对输入输出驻波的高要求。测试结果表明,低噪放模块增益为26 dB,带内增益平坦,输入输出驻波＜1.5,噪声系数＜2 dB,带外抑制度80 dBc,输出1 dB压缩点8 dBm,满足了导航系统接收机前端对低噪放模块的要求。