Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is $>$ 55 dB over a 200 MHz bandwidth centered around 5.25 $~$GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, $-$79 dBm sensitivity, 5.6 dB SSB NF, $-$7$~$ dBm IIP3, $-$18 dB $S_{11}$ and a 1 mm $times$ 2 mm die area in 0.18$ mu{hbox {m}}$ CMOS.      

A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

The Role of Aging on Dynamic Failure Envelopes of OSP-Sn37Pb Interconnects in Plastic Ball Grid Array (PBGA) Packages

This paper quantifies the effect of aging on the durability of printed wiring assemblies (PWAs) subjected to dynamic loading conditions. The test specimen is a FR4 board with a single 256 I/O, full grid, PBGA component at the center. The pad finish on the board and component side of the Sn37Pb eutectic solder interconnects is organic solderability preservative (OSP) and Sn15Pb, respectively. The test matrix is designed to cover one order of magnitude of PWA flexural strain (1E-3 to 1E-2), three orders of magnitude of PWA flexural strain rate (1E-3 to 1E0 ${hbox {s}}^{-1}$), and two aging conditions (as-reflowed and 125 $^{circ}{hbox {C}}$ for 100 h). Fatigue failure envelopes, based on a mechanics-inspired empirical rate-dependent model, are used to characterize the durability in terms of PWA flexural strain and strain rate. A failure site transition zone (FSTZ) is defined in terms of the damage parameters, beyond which the failure site changes from the solder to other parts of the PWA. The combined effect of load amplitude, loading rate, and thermal aging on the FSTZ and solder durability is quantified and presented.      

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits

Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66$times$ average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-$mu$ m process.      

Graphene Nanoribbon Tunnel Transistors

A graphene nanoribbon (GNR) tunnel field-effect transistor (TFET) is proposed and modeled analytically. Ribbon widths between 3 and 10 nm are considered to effect energy bandgaps in the range of 0.46 to 0.14 eV. It is shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing. The transistor achieves 800 $muhbox{A}/muhbox{m}$ on -state current and 26 $hbox{pA}/muhbox{m}$ off-state current, with an effective subthreshold swing of 0.19 mV/dec. Compared to a projected 2009 $n$MOSFET, the GNR TFET can provide 5$times$ higher speed, 20$ times$ lower dynamic power, and 280 000$times$ lower off-state power dissipation. The high performance of GNR TFETs results from their narrow bandgaps and their 1-D nature.      

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

Cyclic Codes and Sequences From Generalized Coulter–Matthews Function

In this paper, we will study the exponential sum $sum_{xin {BBF}_q}chi(alpha x^{(p^k+1)/2}+beta x)$ that is related to the generalized Coulter–Matthews function $x^{(p^k+1)/2}$ with $k/{rm gcd}(m,k)$ odd. As applications, we obtain the following: the correlation distribution of a $p$-ary $m$-sequence and a decimated $m$-sequence of degree ${p^k+1 over 2}$;      

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

As an attempt to considerably reduce the equivalent contact resistivity of Schottky junctions, this letter studies the integration of rare-earth silicides, known to feature the lowest Schottky barriers (SBs) to electrons, coupled with a dopant segregation based on arsenic $(hbox{As}^{+})$ implantation. Both erbium (Er) and ytterbium (Yb) have been considered in the implant-before-silicide (IBS) and implant-to-silicide flavors. It is shown that the two schemes coupled with a limited thermal budget (500 $^{circ}hbox{C}$) produce an SB below the target of 0.1 eV. The implementation of IBS arsenic-segregated $hbox{YbSi}_{1.8}$ junctions in an n-type SB-MOSFET is demonstrated for the first time resulting in a current-drive improvement of more than one decade over the dopant-free counterpart.      

A 3-D High-Frequency Array Based 16 Channel Photoacoustic Microscopy System for In Vivo Micro-Vascular Imaging

This paper discusses the design of a novel photoacoustic microscopy imaging system with promise for studying the structure of tissue microvasculature for applications in visualizing angiogenesis. A new 16 channel analog and digital high-frequency array based photoacoustic microscopy system (PAM) was developed using an Nd:YLF pumped tunable dye laser, a 30 MHz piezo composite linear array transducer, and a custom multichannel receiver electronics system. Using offline delay and sum beamforming and beamsteering, phantom images were obtained from a 6 $mu{hbox {m}}$ carbon fiber in water at a depth of 8 mm. The measured $-6~{rm dB}$ lateral and axial spatial resolution of the system was $100pm 5~mu{hbox {m}}$ and $45pm 5~mu{hbox {m}}$, respectively. The dynamic focusing capability of the system was demonstrated by imaging a composite carbon fiber matrix through a 12.5 mm imaging depth. Next, 2-D in vivo images were formed of vessels around 100 $mu{hbox {m}}$ in diameter in the human hand. Three-dimensional in vivo images were also formed of micro-vessels 3 mm below the surface of the skin in two Sprague Dawley rats.      

Single-Exclusion Number and the Stopping Redundancy of MDS Codes

For a linear block code ${cal C}$, its stopping redundancy is defined as the smallest number of check nodes in a Tanner graph for ${cal C}$, such that there exist no stopping sets of size smaller than the minimum distance of ${cal C}{bf .},$ Schwartz and Vardy conjectured that the stopping redundancy of a maximum-distance separable (MDS) code should only depend on its length and minimum distance.      

High-Speed 2$, times ,$2 Switch for Multiwavelength Silicon-Photonic Networks–On-Chip

We report the fabrication and experimental verification of a multiwavelength high-speed 2$, times ,$ 2 silicon photonic switch for ultrahigh-bandwidth message routing in optical on-chip networks. The structure employs only two microring resonators in order to implement the bar and cross states of the switch. These states are toggled using an optical pump at 1.5-$mu$m wavelengths inplane with the waveguide devices, though electronic, rather than optical, control schemes are envisioned for more complex systems built from these devices. Experiments characterize bit-error-rate performance in the bar and cross states during static and dynamic operation. The all-optical demonstration exhibits the ability of the switch to implement ultra-short transition times ( $≪ $2 ns), high extinction ratios ($>$10 dB), and low power penalties (${sim} 1$ dB) at a data rate of 10 Gb/s. Further performance improvements are expected by using electronic carrier injection via p-i-n diodes surrounding the ring waveguides. The 2$, times ,$2 switching functionality facilitates the design of more complex routing structures, allowing the implementation of high-functionality integrated optical networks.      

A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

Modeling of Distributed RLC Interconnect and Transmission Line via Closed Forms and Recursive Algorithms

This paper presents the closed forms of the state-space models and the recursive algorithms of the transfer function models for fast and accurate modeling of the distributed RLC interconnect and transmission lines, which may be evenly or unevenly distributed. Considered models include the distributed RLC interconnect lines with or without external source and load connection. The effective closed forms and recursive algorithms do not involve any matrix inverse, LU matrix factorization, or matrix multiplication, thus reducing the computation complexity dramatically. Especially, the computation complexity of the closed forms for any evenly or unevenly distributed RLC interconnect line circuits is only O(1) or $ { O}(m)$, respectively, in sense of the scalar multiplication times, where $ { m}ll{ N}$ of the system order. The features of new recursive algorithms are two recursive s-polynomials and the low computation complexity. Examples illustrate the new methods in both time and frequency domains. Comparing with the PSpice, the new methods can dramatically reduce the runtime of the time responses and the Bode plots by 25% – 98.5% in the examples. The results can be applied to the RLC interconnect analysis and model reduction as a key to new approach.      

High-Temperature High-Power Operation of GaInNAs Laser Diodes in the 1220–1240-nm Wavelength Range

We report on the high-temperature performance of high-power GaInNAs broad area laser diodes with different waveguide designs emitting in the 1220–1240-nm wavelength range. Large optical cavity laser structures enable a maximum continuous-wave output power of $>$8.9 W at ${T}=20 ^{circ}$C with emission at 1220 nm and are characterized by low internal losses of 0.5 cm$^{-1}$ compared to 2.9 cm$^{-1}$ for the conventional waveguide structures. High-power operation up to temperatures of 120 $^{circ}$C is observed with output powers of $>$4 W at ${T}=90 ^{circ}$C. This laser diode showed characteristic temperatures of ${T}_{0} =112$ K and ${T}_{1}=378$ K.      

SEChecker: A Sequential Equivalence Checking Framework Based on ${K}$th Invariants

In recent years, considerable research efforts have been devoted to utilizing circuit structural information to improve the efficiency of Boolean satisfiability (SAT) solving, resulting in several efficient circuit-based SAT solvers. In this paper, we present a sequential equivalence checking framework based on a number of circuit-based SAT solving techniques as well as a novel invariant checker. We first introduce the notion of $k$th invariants. In contrast to the traditional invariants that hold for all cycles, $k$ th invariants are guaranteed to hold only after the $k$th cycle from the initial state. We then present a bounded model checker (BMChecker) and an invariant checker (IChecker), both of which are based on circuit SAT techniques. Jointly, BMChecker and IChecker are used to compute the $k$th invariants, and are further integrated in a sequential circuit SAT solver for checking sequential equivalence. Experimental results demonstrate that the new sequential equivalence checking framework can efficiently verify large industrial designs that cannot be verified by existing solutions.      

Robust Precoder Adaptation for MIMO Links With Noisy Limited Feedback

In this paper, we propose two robust limited feedback designs for multiple-input multiple-output (MIMO) adaptation. The first scheme, namely, the combined design jointly optimizes the adaptation, CSIT (channel state information at the transmitter) feedback as well as index assignment strategies. The second scheme, namely, the decoupled design, focuses on the index assignment problem given an error-free limited feedback design. Simulation results show that the proposed framework has significant capacity gain compared to the naive design (designed assuming there is no feedback error). Furthermore, for large number of feedback bits $C_{rm fb}$, we show that under two-nearest constellation feedback channel assumption, the MIMO capacity loss (due to noisy feedback) of the proposed robust design scales like ${cal O}(P_e2^{-{{C_{rm fb}}over{t+1}}})$ for some positive integer $t$. Hence, the penalty due to noisy limited feedback in the proposed robust design approaches zero as $C_{rm fb}$ increases.      

Sharp $p$ -Divisibility of Weights in Abelian Codes Over ${BBZ}/p^d{BBZ}$

A theorem of McEliece on the $p$-divisibility of Hamming weights in cyclic codes over ${BBF}_p$ is generalized to Abelian codes over ${{{BBZ}/p^d{BBZ}}}$. This work improves upon results of Helleseth–Kumar–Moreno–Shanbhag, Calderbank–Li–Poonen, Wilson, and Katz. These previous attempts are not sharp in general, i.e., do not report the full extent of the $p$ -divisibility except in special cases, nor do they give accounts of the precise circumstances under which they do provide best possible results. This paper provides sharp results on $p$-divisibilities of Hamming weights and counts of any particular symbol for an arbitrary Abelian code over ${{{BBZ}/p^d{BBZ}}}$. It also presents sharp results on $2$-divisibilities of Lee and Euclidean weights for Abelian codes over ${{{BBZ}/4{BBZ}}}$.      

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-${rm mu}hbox{m}$ CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a $7.00times 10^{-5}$ bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide $8.84times 10^{-3}$ BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 ${rm mu}hbox{W/MHz}$ of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .