GaAs FET upconverter for TV tuner

The critical part of a broad-band TV tuner, i.e., the upcon-verter was fabricated with simple GaAs IC's. The results obtained were: 1) "Pure" frequency spectrum due to double balanced mixer configuration. 2) Constant conversion gain of 12 ± 2 dB over the entire TV band (50-900 MHz). 3) Good linearity for large signals: Suppression of third-order intermodulation >40 dB for typical bias. 4) Low noise figure (typically 8 dB). These data demonstrate the feasibility of a monolithically integrated single-range TV tuner on GaAs.     

A GaAs up converter integrated circuit for a double conversioncable TV “set-top” tuner

A GaAs up converter integrated circuit used for a double conversion cable TV “set-top” tuner is described. The up converter IC converts the 50 to 550 MHz band to an IF of 700 MHz. The IC meets the linearity and noise figure requirements for a cable TV tuner. It includes an AGC and image reject filter. The reduced component count achieved by using an integrated circuit and the resulting reduction in the size of the tuner, provides potential cost savings over a discrete implementation     

A 48–860 MHz CMOS Low-IF Direct-Conversion DTV Tuner

A CMOS low-IF direct-conversion digital TV (DTV) tuner needs no off-chip harmonic rejection and image filters to receive both terrestrial and cable TV channels in the 48 to 860 MHz frequency range. Complex in-phase and quadrature (I/Q) poly-phase mixing together with coarse active RF filtering suppresses the third-harmonic mixing by 72 dB, and a digital LMS image correlation algorithm reduces the image leakage by 61 dB. A global AGC scheme keeps the signal level in the down-conversion mixer constant, and warrants the RF front-end linearity with strong blockers. Anti-aliasing and digital channel filters are made digitally programmable so that DTV standards with 6–8 MHz channel bandwidths can be supported. The measured system noise figure is 4–7 dB over the whole TV band. When measured at 500 MHz, the sensitivity is $-$86 dBm with ATSC-T 8-VSB signal, and the MER is 31.5 dB with actual J.83/B 256-QAM signal from a commercial CATV source. The chip implemented in 0.18 $mu{hbox{m}}$ CMOS occupies 5$times {hbox{5 mm}}^{2}$, and consumes 750 mW at 1.8 V.      

CMOS宽带可编程增益低噪声放大器

给出了一种可应用于中国移动多媒体广播(CMMB)调谐器的宽带(470~860 MHz)可编程增益低噪声放大器。该电路在UMC 0.18μm RF CMOS工艺下实现,芯片面积为0.37 mm2(不包括ESD pad)。芯片测试结果表明,在1.8 V的电源电压下功耗为30.2 mW,该电路可实现-6.8~32.4 dB的增益动态变化范围,0.5 dB步长,最高增益下单端信号噪声系数小于3.8 dB。     

An integrated up-converter circuit in 0.8 μm SiGe technology for TV applications

This paper describes an up-converter circuit for a TV tuner chain that can be implemented in both analog and digital TV systems. The circuit is integrated into a low cost standard two metal layer 0.8 μm SiGe technology and is composed with class AB Gilbert cell based active mixer and differential voltage-controlled oscillator (VCO). The use of a high quality balanced inductor in the VCO allows achieving a measured oscillator phase noise of −104.2 dBc/Hz at 100 kHz from the carrier. The frequency conversion is from TV standard IF to RF. The results obtained in a frequency up-conversion from 36 to 1775 MHz are: a conversion gain of −2.25 dB, a noise figure of 14.4 dB and an OIP3 value of 9.1 dBm. The core power consumption is 33 mA from 5 V power supply.     

A Highly Linear Wideband Up-Conversion Differential CMOS Micromixer Using IMD3 Cancellation for a Digital TV Tuner IC

In this letter, a highly linear wideband up-conversion differential CMOS micromixer with a linearized transconductor employing a third order intermodulation (IMD3) cancellation technique for a digital TV tuner IC is proposed and designed. It is fabricated in a 0.18 $mu$ m CMOS process and draws 22 mA from a 1.8 V supply voltage. It shows a voltage gain of more than 6 dB, a noise figure lower than 11.9 dB, an IIP2 of more than 57 dBm, and an IIP3 of more than 18 dBm for the entire input band from 48 to 860 MHz.      

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor

A fully integrated direct conversion DVB-H tuner is realized in a 0.5-mum SiGe BiCMOS technology. To meet the stringent linearity requirement while keeping low power consumption, novel linearization techniques for a variable-gain low-noise amplifier (VG-LNA) and a mixer are proposed. The proposed linearized VG-LNA has a variable gain range of over 50 dB, noise figure of less than 2.6 dB over the frequency range from 200 to 1000 MHz, and IIP3 of more than -10 dBm at a current consumption of 2.1 mA. The quadrature mixer with the proposed linearization technique achieves OIP3 of more than 25 dBm at a current consumption of 5 mA. In addition, a new offset-cancel feedback is introduced for the baseband block of a direct conversion receiver, which keeps the high-pass cutoff frequency independent of the baseband VGA gain. The fabricated tuner IC satisfies all the DVB-H requirements at a power consumption of 184 mW     

一种用于超高频RFID阅读器的正交下变频混频器的分析与设计

分析了共用跨导级的正交下变频混频器的性能,包括电压转换增益、线性度、噪声系数和镜象抑制比,分析表明其在电流开关模式下比传统的Gilbert混频器对具有更好的性能.设计并优化了一个基于共用跨导级结构的用于超高频RFID阅读器的正交下变频混频器.在915MHz频段上,该混频器测得12.5dB的转换增益,10dBm的ⅡP3,58dBm的ⅡP2和17.6dB的SSB噪声系数.芯片采用0.18μm 1P6M RF CMOS工艺实现,在1.8V的电源电压下仅消耗3mA电流.     

The Comparative Performance of FET and Bipolar Transistors at VHF

The relative performance of FET and bipolar transistors 200 MHz AGC amplifiers in a TV tuner is discussed. It is concluded that both junction and insulated gate FET's have better overload capability than the bipolar transistor though they have a lower stable gain. The noise figure of the IG FET increases less rapidly with AGC than does the noise figure of the bipolar transistor. The performance of all three semiconductor devices is compared with that of a popular vacuum tube (6DS4) in its tuner.     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

SiP Tuner With Integrated LC Tracking Filter for Both Cable and Terrestrial TV Reception

A silicon tuner has been designed for the reception of analog or digital TV signals from a cable or a terrestrial network. It exhibits 5 dB NF over the 42-870 MHz frequency range and integrates a self-calibrated LC tracking filter. This allows 55 dB video SNR under fully loaded spectrum conditions. The (N + 1) image channel is rejected by more than 62 dB thanks to a fully integrated full complex mixer with auto calibration. The 5.7 mm² active die is fabricated in 40-GHz f_T BiCMOS 0.25 mum technology and dissipates 780 mW running from a 3.3 V supply.     

A 2.4-GHz sub-mW CMOS receiver front-end for wireless sensors network

A 2.4-GHz fully integrated CMOS receiver front-end using current-reused folded-cascode circuit scheme is presented. A configuration utilizing vertically stacked low-noise amplifier (LNA) and a folded-cascode mixer is proposed to improve both conversion gain and noise figure suitable for sub-mW receiver circuits. The proposed front-end achieves a conversion gain of 31.5dB and a noise figure of 11.8dB at 10MHz with 500-/spl mu/A bias current from a 1.0-V power supply. The conversion gain and noise figure improvements of the proposed front-end over a conventional merged LNA and single-balanced mixer are 11dB and 7.2dB at 10MHz, respectively, with the same power consumption of 500/spl mu/W.     

A 0.35μm CMOS Mixer for 2.45-GHz RFID Application

A RF mixer with both low noise and high linearity is designed,operating at 2.45-GHz ISM band for RFID application.The designed mixer uses an optimal input matching network and the carefully chosen sizes of transistors,also with the appropriate bias point,to improve the noise figure(NF).Also,with a resonant LC loop as the current source and a parallel PMOS-resistor as the load,the mixer has a high linearity.The post simulation results show that the single side- band noise figure of 8.57 dB,conversion gain of 10.02 dB,input 1-dB compression point(P-1dB)of-8.33 dBm,and input third-order intercept point(IIP3)of 5.35 dBm.     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

A low-voltage ultra-wideband down-conversion mixer with improved power conversion gain

This article presents a wideband mixer using a TSMC 0.18?µm complementary metal-oxide semiconductor technology process for ultra-wideband (UWB) system applications. The measured 3-dB radio frequency (RF) bandwidth is from 3 to 8.4?GHz with an intermediate frequency of 10?MHz. The measurement results of the proposed mixer achieve 8.1?dB average power conversion gain ?5?dBm input third-order intercept point (IIP3) at 7.4?GHz and 12.4–13.3?dB double side band noise figure. The total dc power consumption of this mixer including output buffers is 3.18?mW from a 1?V supply voltage. The output current buffer consumption is about 2.26?mW with an excellent local oscillator-RF isolation of up to 40?dB at 5?GHz. The article presents a mixer topology that is greatly suitable for low-power operation in UWB system applications.     

A Weak-Inversion Low-Power Active Mixer for 2.4 GHz ISM Band Applications

This work describes a fully integrated active mixer designed in 0.18 $mu{rm m}$ CMOS technology for 2.4 GHz Industrial, Scientific and Medical (ISM) band applications. The mixer uses a source driven local oscillator (LO) to integrate the RF-LO buffering with the active mixer, and weakly inverted input MOSFETs to improve the gain and noise performance. The double-balanced quadrature mixer has a measured conversion gain of 32 dB with a double sideband (DSB) noise figure (NF) of 8.5 dB at 30 MHz intermediate frequency (IF) while consuming only 0.56 mA of current from a 1.8 V supply.      

一种用于超高频RFID阅读器的正交下变频混频器的分析与设计

分析了共用跨导级的正交下变频混频器的性能,包括电压转换增益、线性度、噪声系数和镜象抑制比,分析表明其在电流开关模式下比传统的Gilbert混频器对具有更好的性能.设计并优化了一个基于共用跨导级结构的用于超高频RFID阅读器的正交下变频混频器.在915MHz频段上,该混频器测得12.5dB的转换增益,10dBm的IIP3 ,58dBm的IIP2和17.6dB的SSB噪声系数.芯片采用0.18μm 1P6M RF CMOS工艺实现,在1.8V的电源电压下仅消耗3mA电流.     

A CMOS Harmonic Rejection Mixer With Mismatch Calibration Circuitry for Digital TV Tuner Applications

A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-$mu$m CMOS technology. Odd harmonic mixing in the 48–862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over ${-}{hbox {60}}$ dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of ${-}{hbox {30}}$ to ${-}{hbox {40}}$ dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than ${-}{hbox {70}}$ dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.      

An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Sibipolar technology

An all-band TV tuner IC with an on-chip PLL and a high-voltage output stage is developed. The use of a self-aligned bipolar technology called high-voltage compatible sidewall base contact structure (HV-SICOS) allows the integration of 1-GHz analog circuits, 1-GHz low-power ECL-I²L PLL circuits, and a 0.5- to 30-V tuning diode bias current on the same chip. The analog block has a VCO and mixer pair for the VHF/CATV and another pair for the UHF bands, a UHF input amplifier, an IF amplifier, and a VCO signal switching circuit. To suppress the digital noise level for mixed analog/digital mode operation, the PLL is constructed with high-speed ECL circuits for divide-by-four and dual modulus prescalers, and low-power I²L circuits. An isolation area is placed between the analog and digital blocks. Conversion gain of 24 dB for VHF/CATV and 33 dB for UHF, a noise figure of 10 dB, and 1% cross modulation of 95 dB-μV are obtained. This IC operates with a total power dissipation of 200 mW on a 3-mm×4-mm chip     

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 $muhbox{m}$ CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under ${- 9}~{rm dB}$ in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 ${rm mm}^{2}$.