RESURF LDMOSFET with a trench for SOI power integrated circuits

A new structure of RESURF LDMOSFET is proposed, based on silicon-on-insulator, to improve the characteristics of the breakdown voltage and the specific on-resistance, where a trench is applied under the gate in the drift region. A trench is used to reduce the electric field under the gate when the concentration of the drift region is high, thereby increasing the breakdown voltage and reducing the specific on-resistance. Detailed numerical simulations demonstrate the characteristics of this device and indicate an enhancement on the performance of the breakdown voltage and the specific on-resistance in comparison with an optimal conventional device with LOCOS under the gate.     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

A floating RESURF (FRESURF) LD-MOSFET device concept

This letter reports a novel device concept, which is an extension of the conventional reduced surface field (RESURF) concept. A heavily doped n-type floating region is introduced into the conventional device structure which allows the breakdown capability of the device to be increased significantly while at the same time making it high-side capable. This floating RESURF (FRESURF) device concept allows the realization of significantly higher breakdown voltage in a thin epitaxy based power integrated circuit (IC) technology. A FRESURF lateral double-diffused power MOS transistor is designed, fabricated and reported for the first time with breakdown voltages as high as 90 V as opposed to 55 V obtained from conventional device sharing same process and drift region doping.     

Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices

A simple one-dimensional (1-D) analytical solution method for analyzing and determining the breakdown properties of reduced surface field (RESURF) lateral devices is presented. The solution demonstrates quantitatively and qualitatively the reshaping and reduction of the electric field and its dependence on the device/process key parameters. The solution is based on a simple and physical charge-sharing approach that takes into account the modulation of the lateral depletion layer spreading caused by the vertical depletion extension, and therefore transforms the inherent two-dimensional effects into a simple 1-D equivalent. It also provides a reasonable insight on the breakdown voltage sensitivity of lateral RESURF devices to key device/process parameters that other researchers failed to provide. Using the technique, device designers can set and choose the optimal processing window of the device's critical layers to yield high breakdown voltages. The results obtained using the proposed solution method agree well with the experimental and simulation results.     

SOI RESURF器件高压互连线效应的二维解析模型

高压互连线效应是影响集成功率器件性能的重要因素之一。首先提出一个高压互连线效应对SOI横向高压器件的漂移区电势和电场分布影响的二维解析模型,进而得到漂移区在不完全耗尽和完全耗尽情况下的器件击穿电压解析表达式,而后利用所建立的模型,研究器件结构参数对击穿特性的影响规律,定量揭示在高压互连线作用下器件击穿多生在阳极PN结的物理本质,指出通过优化场氧厚度可以弱化高压互连线对器件击穿的负面影响,并给出用于指导设计的理论公式。模型的正确性通过半导体二维器件仿真软件MEDICI进行了验证。     

A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact

A novel trench lateral power MOSFET with a trench bottom source contact (TLPM/S) is proposed, fabricated, characterized, and compared with the equivalent TLPM with a trench bottom drain contact (TLPM/D). The TLPM/S is formed along the sidewalls of the trenches so as to reduce the device pitch and realize very small on-resistance per unit area. A total of eight masks are used for fabricating the device. Since the gate electrode and the trench bottom source contact are formed by self-aligning to the trench sidewalls, the device pitch is reduced. Using a line width of 0.6 /spl mu/m, the fabricated TLPM/S, whose device pitch is 3.0 /spl mu/m, exhibits a specific on-resistance of 60 m/spl Omega/-mm/sup 2/ for a breakdown voltage of 73 V, which is close to the estimated silicon limit for this voltage class of devices. Due to reduced Miller capacitance, the TLPM/S exhibits excellent switching performance, and is approximately 50% faster than the equivalent TLPM/D.     

1300-V 6H-SiC lateral MOSFETs with two RESURF zones

A two-zone, lateral RESURF field 6H-SiC MOSFET with breakdown voltage as high as 1300 V and specific on-resistance of 160 m/spl Omega//spl middot/cm/sup 2/ has been fabricated. These MOSFETs exhibit stable and reversible breakdown indicating avalanche breakdown in SiC that has not been reported in earlier lateral SiC MOSFETs.     

A high-speed, high-sensitivity silicon lateral trench photodetector

We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed and high responsivity. The photodetector, fabricated with fully VLSI compatible processes, exhibits a 6-dB bandwidth of 1.5 GHz at 3.0 V and an external quantum efficiency of 68% at 845 nm wavelength. A photoreceiver with a wire-bonded lateral trench detector and a BiCMOS transimpedance amplifier demonstrates excellent operation at 2.5 Gb/s data rate and 845 nm wavelength with only a 3.3 V bias     

A novel numerical model for SOI devices

The Poisson's equation governing the potential distribution of semiconductor-on-insulator (SOI) structures is solved by a novel numerical technique. In this efficient method, no grid-points need to be assigned for all the insulator regions such as the surface oxide layer, buried oxide layer, and sapphire layer.     

阶梯变掺杂漂移区高压SOI RESURF结构耐压机理研究

研究了阶梯变掺杂漂移区高压SOI RESURF(Reduce SURface Field)结构的器件几何形状和物理参数对器件耐压的影响;发现并解释了该结构纵向击穿时,耐压与浓度关系中特有的“多RESURF平台”现象。研究表明,阶梯变掺杂漂移区结构能明显改善表面电场分布,提高耐压,降低导通电阻,增大工艺容差;利用少数分区,能得到接近线性变掺杂的耐压,降低了工艺难度。     

基于介质电场增强理论的SOI横向高压器件与耐压模型

SOI(Silicon On Insulator)高压集成电路(High Voltage Integrated Circuit,HVIC)因其具有高速、低功耗、抗辐照以及易于隔离等优点而得以广泛应用。作为SOIHVIC的核心器件,SOI横向高压器件较低的纵向击穿电压,限制了其在高压功率集成电路中的应用。为此,国内外众多学者提出了一系列新结构以提高SOI横向高压器件的纵向耐压。但迄今为止,SOI横向高压器件均采用SiO2作为埋层,且实用SOI器件击穿电压不超过600V;同时,就SOI横向器件的电场分布和耐压解析模型而言,现有的模型仅针对具有均匀厚度埋氧层和均匀厚度漂移区的SOI器件建立,而且没有一个统一的理论来指导SOI横向高压器件的纵向耐压设计。笔者围绕SOI横向高压器件的耐压问题,从耐压理论、器件结构和耐压解析模型几方面进行了研究。基于SOI器件介质层电场临界化的思想,提出介质电场增强ENDIF(Enhanced Dielectric LayerField)理论。在ENDIF理论指导下,提出三类SOI横向高压器件新结构,建立相应的耐压解析模型,并进行实验。(1)ENDIF理论对现有典型横向SOI高压器件的纵向耐压机理统一化ENDIF理论的思想是通过增强埋层电场而提高SOI横向器件的纵向耐压。ENDIF理论给出了增强埋层电场的三种途径:采用低εr(相对介电常数)介质埋层、薄SOI层和在漂移区/埋层界面引入电荷,并获得了一维近似下埋层电场和器件耐压的解析式。ENDIF理论可对现有典型SOI横向高压器件的纵向耐压机理统一化,它突破了传统SOI横向器件纵向耐压的理论极限,是优化设计SOI横向高压器件纵向耐压的普适理论。(2)基于ENDIF理论,提出以下三类SOI横向高压器件新结构,并进行理论和实验研究①首次提出低εr型介质埋层SOI高压器件新型结构及其耐压解析模型低εr型介质埋层SOI高压器件包括低εr介质埋层SOI高压器件、变εr介质埋层SOI高压器件和低εr介质埋层PSOI(PartialSOI)高压器件。该类器件首次将低介电系数且高临界击穿电场的介质引入埋层或部分埋层,利用低εr介质增强埋层电场、变εr介质调制埋层和漂移区电场而提高器件耐压。通过求解二维Poisson方程,并考虑变εr介质对埋层和漂移区电场的调制作用,建立了变εr介质埋层SOI器件的耐压模型,由此获得RESURF判据。此模型和RESURF判据适用于变厚度埋层SOI器件和均匀介质埋层SOI器件,是变介质埋层SOI器件(包括变εr和变厚度介质埋层SOI器件)和均匀介质埋层SOI器件的统一耐压模型。借助解析模型和二维器件仿真软件MEDICI研究了器件电场分布和击穿电压与结构参数之间的关系。结果表明,变εr介质埋层SOI高压器件的埋层电场和器件耐压可比常规SOI器件分别提高一倍和83%,当源端埋层为高热导率的Si3N4而不是SiO2时,埋层电场和器件耐压分别提高73%和58%,且器件最高温度降低51%。解析结果和仿真结果吻合较好。②提出并成功研制电荷型介质场增强SOI高压器件笔者提出的电荷型介质场增强SOI高压器件包括:(a)双面电荷槽SOI高压器件和电荷槽PSOI高压器件,其在埋氧层的一侧或两侧形成介质槽。根据ENDIF理论,槽内束缚的电荷将增强埋层电场,进而提高器件耐压。电荷槽PSOI高压器件在提高耐压的基础上还能降低自热效应;(b)复合埋层SOI高压器件,其埋层由两层氧化物及其间多晶硅构成。该器件不仅利用两层埋氧承受耐压,而且多晶硅下界面的电荷增强第二埋氧层的电场,因而器件耐压提高。开发了基于SDB(Silicon Direct Bonding)技术的非平面埋氧层SOI材料的制备工艺,并研制出730V的双面电荷槽SOILDMOS和760V的复合埋层SOI器件,前者埋层电场从常规结构的低于120V/μm提高到300V/μm,后者第二埋氧层电场增至400V/μm以上。③提出薄硅层阶梯漂移区SOI高压器件新结构并建立其耐压解析模型该器件的漂移区厚度从源到漏阶梯增加。其原理是:在阶梯处引入新的电场峰,新电场峰调制漂移区电场并增强埋层电场,从而提高器件耐压。通过求解Poisson方程,建立阶梯漂移区SOI器件耐压解析模型。借助解析模型和数值仿真,研究了器件结构参数对电场分布和击穿电压的影响。结果表明:对tI=3μm,tS=0.5μm的2阶梯SOI器件,耐压比常规SOI结构提高一倍,且保持较低的导通电阻。仿真结果证实了解析模型的正确性。     

有n缓冲层SOI RESURF结构的电场分布解析模型

提出了有n缓冲层SOI RESURF结构的电场分布解析模型,采用MEDICI数值仿真,验证了上述模型的正确性。基于所建立的解析模型,获得了缓冲层的最优杂质浓度分布,提出了提高SOI RESURF结构耐压的缓冲层分段变掺杂新结构。     

High performance SOI CMOS pixel sensor with surrounding N+ trench electrode

In this paper, an advanced SOI CMOS pixel (ASCP) detector structure with deep N+ trench electrode is researched and simulated. For this pixel structure, the N+ trench cathode surrounds the P+ trench anode, and they are both connected from the topside. The cathode is in the function of charge share shielding, it isolates the neighbor pixels, and avoids the crosstalk happening of electron hole pairs. Furthermore, the parallel trench electrodes between anode and cathode have reduced the fully depleted voltage, and the bias voltage can be controlled from the core I/O interface. In addition, the ASCP has the better radiation resistance capacity as compared with the Conventional SOI CMOS pixel detector and the Three-Dimension (3D) CMOS detector, due to the low fully depleted voltage and short carrier drift distance. Numerical simulation results show that the ASCP detector has the better charge collecting capacity in low driving voltage, and it is more suitable to detect the back-illumination X-ray ⁵⁵Fe.     

场板SOI RESURF LDMOS表面势场分布解析模型

以往对SOI器件的建模基本上基于漂移区全耗尽的假设,且大多未考虑场板对表面势场分布的影响。通过分区求解二维泊松方程,建立了场板SOI RESURF LDMOS表面电势和表面电场分布解析模型。该模型同时考虑了栅场板和漏场板的作用,既适用于漂移区全耗尽的情况,也适用于漂移区不全耗尽的情况。利用此模型和半导体器件仿真工具Silvaco,详细探讨了器件在不同偏压下栅场板和漏场板对漂移区表面电势和电场分布的影响。解析模型结果与数值仿真结果吻合良好,验证了模型的准确性。     

Characteristics of MSM photodetectors with trench electrodes onp-type Si wafer

U-grooved metal-semiconductor-metal photodetectors (UMSM-PD's) having various trench depths of interdigitated electrodes and an intrinsic hydrogenated amorphous silicon (i-a-Si:H) to c-Si heterojunction have been fabricated successfully on a p-type [100] Si wafer. The U-grooved structures on c-Si were achieved with a simple orientation-dependent etching (ODE) process. Some important characteristics of the obtained UMSM-PDs are presented and discussed. An UMSM-PD with a 70 nm i-a-Si:H overlayer, 1.45 μm-deep recessed electrodes, and 3 μm finger width and spacing, had a full width at half maximum (FWHM) of 50.6 ps and a full-time of 132 ps for its temporal response under a bias of 15 V. The significant improvements of transient response for UMSM-PD, as compared to the conventional one, were attributed to the trench electrodes resulted in a stronger lateral electric field in the light absorption region of photodetector. At a bias of 20 V, this UMSM-PD had a responsivity of 0.25 A/W as measured with an 0.83-μm incident semiconductor laser, a high photo/dark current ratio about 2000, and an internal quantum efficiency of 36%. This high photo/dark current ratio would be due to the additional i-a-Si:H overlayer on Si wafer. These mentioned performances were much better than those of the conventional Si-based planar MSM-PD     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.     

埋氧层固定界面电荷对RESURF SOI功率器件击穿特性的影响

通过求解具有界面电荷边界条件的二维泊松方程，建立了埋氧层固定界面电荷Qf对RESURF SOI功率器件二维电场和电势分布影响的解析模型。解析结果与半导体器件模拟器MEDICI数值分析结果相吻合。在此基础上，分别研究了Qf对RESURF SOI功率器件横向和纵向击穿特性的影响规律。在横向，讨论了不同硅膜厚度、氧层厚度和漂移区长度情况下Qf对表面电场分布的影响；在纵向，通过分析硅膜内的场和势的分布，提出了临界埋氧层固定界面电荷密度的概念，这是导致器件发生失效的最低界面电荷密度。     

Behavior of hot carrier generation in power SOI LDNMOS with shallow trench isolation (STI)

In this work, we investigated the hot carrier (HC) generation of power silicon-on-insulator (SOI) lateral double-diffused N-type MOSFETs (LDNMOSFET) with shallow trench isolation (STI) structure under different biasing conditions. Experimental measurements of drain and substrate currents are done. Two-dimensional (2-D) device simulation is performed to provide a better insight on the electrical behaviors of the device by looking at the electric-field (EF), electron current density (J_E) and impact ionization generation rate (R_II) distributions in the devices. The high R_II site is found to be near the STI corner instead of near the channel or field oxide area close to the gate surface in standard small signal MOSFET.     

Numerical analysis of SOI LDMOS using a recessed source and a trench drain

A new SOI LDMOS using a recessed source and a trench drain was proposed to improve the on-characteristics at a given breakdown voltage. On-resistance and breakdown voltages of the proposed LDMOS are investigated by the two-dimensional simulator, MEDICI. The simulation results show that the on-resistance of the proposed and the conventional LDMOS are 76.3 and 129.5 mΩ mm², respectively. The on-resistance of the proposed LDMOS decreases by 41% compared to that of the conventional LDMOS at the same breakdown voltage of 36.5 V.