RESURF LDMOSFET with a trench for SOI power integrated circuits

A new structure of RESURF LDMOSFET is proposed, based on silicon-on-insulator, to improve the characteristics of the breakdown voltage and the specific on-resistance, where a trench is applied under the gate in the drift region. A trench is used to reduce the electric field under the gate when the concentration of the drift region is high, thereby increasing the breakdown voltage and reducing the specific on-resistance. Detailed numerical simulations demonstrate the characteristics of this device and indicate an enhancement on the performance of the breakdown voltage and the specific on-resistance in comparison with an optimal conventional device with LOCOS under the gate.     

一种RESURF效应增强的高压低阻槽型SOI LDMOS

本文提出一种RESURF效应增强（Enhanced RESURF Effect）的高压低阻SOI LDMOS（ER-LDMOS）新结构,并研究其工作机理。ER-LDMOS的主要特征是：漂移区中具有氧化物槽;氧化物槽靠近体区一侧具有P条;氧化物槽下方的N型漂移区中具有埋P层。首先,从体区延伸到氧化物槽底部的P条,不仅起到纵向结终端扩展的作用,而且具有纵向RESURF效果,此二者都优化体内电场分布且提高漂移区掺杂浓度;其次,埋P层在漂移区中形成triple RESURF效果,能够进一步优化体内电场并降低导通电阻;第三,漂移区中的氧化物槽沿纵向折叠漂移区,减小了器件元胞尺寸,进一步降低比导通电阻;第四,P条、埋P层、氧化物槽和埋氧层对N型漂移区形成多维耗尽作用,实现增强的RESURF效应,可达到提高漂移区掺杂浓度与优化电场分布的目的,从而降低导通电阻且提高器件耐压。仿真结果表明,在相同的器件尺寸参数下,与常规槽型SOI LDMOS相比,ER-LDMOS击穿电压提高67%,比导通电阻降低91%。     

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_sp is reduced from 16.5 to 13.8 mΩ·cm² in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV²/R_on.It reduces R_sp by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.     

一种新型高压Triple RESURF SOI LDMOS

提出了一种新型Triple RESURF SOI LDMOS结构,该结构有一个Ｐ型埋层。首先,耗尽层能够在Ｐ型埋层的上下同时扩展与Triple RESURF机理相同,使得漂移区浓度提高,导通电阻降低。其次,当漂移区浓度较高时,Ｐ型埋层起到了降低体内电场的作用,并能够提高漏端纵向电场使得其电场分布更加均匀从而耐压增加。Triple RESURF结构在SOI LDMOS中首次提出。在６微米厚的SOI层以及２微米厚的埋氧层中获得了耐压300V的Triple RESURF SOI LDMOS,其导通电阻从Double RESURF SOI LDMOS的17.2mΩ.cm2降低到13.8mΩ.cm2。当外延层厚度增加时, Triple RESURF结构的效果更加明显,在相同耐压下,相对于Double RESURF,该结构能够在400V和550V的SOI LDMOS中分别降低29%和38%的导通电阻。     

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...     

Process optimization of a deep trench isolation structure for high voltage SOI devices

In this work, the process reasons for weak point formation of the deep trench on SOI wafer have been analyzed in detail. The optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of silicon on the surface of buried oxide caused by fringe effect; the other is slowly growth rate of isolation oxide in the concave silicon corner of trench bottom. In order to improve the isolation performance of deep trench, two feasible ways for optimizing trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corner at weak point, increasing the applied voltage by 15-20V at the same leakage current. The proposed new trench isolation process has been verified in foundry’s 0.5-μm HV SOI technology.     

SOI基双级RESURF二维解析模型

提出了SOI基双级RESURF二维解析模型.基于二维Poisson方程,获得了表面电势和电场分布解析表达式,给出了SOI的双级和单级RESURF条件统一判据,得到RESURF浓度优化区(DOR,doping optimal region),研究表明该判据和DOR还可用于其他单层或双层漂移区结构.根据此模型,对双级RESURF结构的降场机理和击穿特性进行了研究,并利用二维器件仿真器MEDICI进行了数值仿真.以此为指导成功研制了耐压为560V和720V的双级RESURF高压SOI LDMOS.解析解、数值解和实验结果吻合得较好.     

SOI基双级RESURF二维解析模型

提出了SOI基双级RESURF二维解析模型．基于二维Poisson方程，获得了表面电势和电场分布解析表达式，给出了SOI的双级和单级RESURF条件统一判据，得到RESURF浓度优化区(DOR，doping optimal region）,研究表明该判据和DOR还可用于其他单层或双层漂移区结构．根据此模型，对双级RESURF结构的降场机理和击穿特性进行了研究，并利用二维器件仿真器MEDICI进行了数值仿真．以此为指导成功研制了耐压为560V和720V的双级RESURF高压SOI LDMOS．解析解、数值解和实验结果吻合得较好．     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

A charge allocating model for the breakdown voltage calculation and optimization of the lateral RESURF devices

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration (per unit area) of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.     

SOI硅膜厚度对RESURF LDMOS参数的影响

对SOI LDMOS进行了建模,得到了器件各主要参数的最优值与SOI硅膜厚度的关系式.以此为基础用专业软件Medici和Tsuprem-4对器件进行了模拟,得到了最优漂移区浓度、最优击穿电压等参数随SOI硅膜厚度的变化曲线,这些结果对实际器件的设计以及工艺生产具有参考意义.     

SOI硅膜厚度对RESURF LDMOS参数的影响

对SOI LDMOS进行了建模,得到了器件各主要参数的最优值与SOI硅膜厚度的关系式．以此为基础用专业软件Medici和Tsuprem4对器件进行了模拟,得到了最优漂移区浓度、最优击穿电压等参数随SOI硅膜厚度的变化曲线,这些结果对实际器件的设计以及工艺生产具有参考意义．     

A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact

A novel trench lateral power MOSFET with a trench bottom source contact (TLPM/S) is proposed, fabricated, characterized, and compared with the equivalent TLPM with a trench bottom drain contact (TLPM/D). The TLPM/S is formed along the sidewalls of the trenches so as to reduce the device pitch and realize very small on-resistance per unit area. A total of eight masks are used for fabricating the device. Since the gate electrode and the trench bottom source contact are formed by self-aligning to the trench sidewalls, the device pitch is reduced. Using a line width of 0.6 /spl mu/m, the fabricated TLPM/S, whose device pitch is 3.0 /spl mu/m, exhibits a specific on-resistance of 60 m/spl Omega/-mm/sup 2/ for a breakdown voltage of 73 V, which is close to the estimated silicon limit for this voltage class of devices. Due to reduced Miller capacitance, the TLPM/S exhibits excellent switching performance, and is approximately 50% faster than the equivalent TLPM/D.     

SOI RESURF器件高压互连线效应的二维解析模型

高压互连线效应是影响集成功率器件性能的重要因素之一。首先提出一个高压互连线效应对SOI横向高压器件的漂移区电势和电场分布影响的二维解析模型,进而得到漂移区在不完全耗尽和完全耗尽情况下的器件击穿电压解析表达式,而后利用所建立的模型,研究器件结构参数对击穿特性的影响规律,定量揭示在高压互连线作用下器件击穿多生在阳极PN结的物理本质,指出通过优化场氧厚度可以弱化高压互连线对器件击穿的负面影响,并给出用于指导设计的理论公式。模型的正确性通过半导体二维器件仿真软件MEDICI进行了验证。     

A floating RESURF (FRESURF) LD-MOSFET device concept

This letter reports a novel device concept, which is an extension of the conventional reduced surface field (RESURF) concept. A heavily doped n-type floating region is introduced into the conventional device structure which allows the breakdown capability of the device to be increased significantly while at the same time making it high-side capable. This floating RESURF (FRESURF) device concept allows the realization of significantly higher breakdown voltage in a thin epitaxy based power integrated circuit (IC) technology. A FRESURF lateral double-diffused power MOS transistor is designed, fabricated and reported for the first time with breakdown voltages as high as 90 V as opposed to 55 V obtained from conventional device sharing same process and drift region doping.     

用于横向RESURF器件击穿电压优化的电荷分配模型

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF （reduced surface field） structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration （per unit area） of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.     

Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices

A simple one-dimensional (1-D) analytical solution method for analyzing and determining the breakdown properties of reduced surface field (RESURF) lateral devices is presented. The solution demonstrates quantitatively and qualitatively the reshaping and reduction of the electric field and its dependence on the device/process key parameters. The solution is based on a simple and physical charge-sharing approach that takes into account the modulation of the lateral depletion layer spreading caused by the vertical depletion extension, and therefore transforms the inherent two-dimensional effects into a simple 1-D equivalent. It also provides a reasonable insight on the breakdown voltage sensitivity of lateral RESURF devices to key device/process parameters that other researchers failed to provide. Using the technique, device designers can set and choose the optimal processing window of the device's critical layers to yield high breakdown voltages. The results obtained using the proposed solution method agree well with the experimental and simulation results.     

A high-speed, high-sensitivity silicon lateral trench photodetector

We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed and high responsivity. The photodetector, fabricated with fully VLSI compatible processes, exhibits a 6-dB bandwidth of 1.5 GHz at 3.0 V and an external quantum efficiency of 68% at 845 nm wavelength. A photoreceiver with a wire-bonded lateral trench detector and a BiCMOS transimpedance amplifier demonstrates excellent operation at 2.5 Gb/s data rate and 845 nm wavelength with only a 3.3 V bias     

A novel numerical model for SOI devices

The Poisson's equation governing the potential distribution of semiconductor-on-insulator (SOI) structures is solved by a novel numerical technique. In this efficient method, no grid-points need to be assigned for all the insulator regions such as the surface oxide layer, buried oxide layer, and sapphire layer.     

1300-V 6H-SiC lateral MOSFETs with two RESURF zones

A two-zone, lateral RESURF field 6H-SiC MOSFET with breakdown voltage as high as 1300 V and specific on-resistance of 160 m/spl Omega//spl middot/cm/sup 2/ has been fabricated. These MOSFETs exhibit stable and reversible breakdown indicating avalanche breakdown in SiC that has not been reported in earlier lateral SiC MOSFETs.