Constant current stress of lightly Al-doped Ta2O5

The response of lightly Al-doped Ta₂O₅ stacked films (6 nm) to constant current stress (CCS) under gate injection (current stress in the range of 1 to 30 mA/cm² and stressing time of 50–400 s) has been investigated. The stress creates positive oxide charge, which is assigned to oxygen vacancies but it does not affect the dielectric constant of the films. The most sensitive parameter to the stress is the leakage current. Different degradation mechanisms control the stress-induced leakage current (SILC) in dependence on both the stress conditions and the applied measurement voltage. The origin of SILC is not the same as that in pure and Ti- or Hf-containing Ta₂O₅. The well known charge trapping in pre-existing traps operates only at low level stress resulting in small SILC at accumulation. The new trap generation plays a key role in the SILC degradation and is the dominant mechanism controlling the SILC in lightly Al-doped Ta₂O₅ layers.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

The understanding of the memory nature and mechanism of the Ta2O5-gate-dielectric-based organic phototransistor memory

The memory nature and mechanism of the Ta₂O₅-gate-dielectric-based organic phototransistor memory (OPTM) have been studied. The UV–Vis absorption spectra and the X-ray photoelectron spectroscopy indicate that Ta₂O₅ owns positive interfacial charge because of the existence of Ta–OH. The hydroxide results in oxygen deficiency in Ta₂O₅ which is proposed to trap electrons. The characteristics of Ta₂O₅-based capacitor and the energy level alignment at Ta₂O₅–pentacene interface reveal that the electron-injection process is favorable which stimulates the electron-trapping process in Ta₂O₅. The Kelvin probe force microscopy of the Ta₂O₅-pentacene interface certificates the electron-injection and electron-trapping processes as well. It is the positive charges in Ta₂O₅ and energy level alignment that lead to the memory effect of Ta₂O₅-gate-dielectric-based OPTM. Compared to Ta₂O₅, polymethyl methacrylate (PMMA) does not have so strong a positive interface. Accordingly, PMMA films of different thickness are adopted on Ta₂O₅ to tune the Ta₂O₅-pentacene interface, offering control of the memory properties including the memory window and retention time. The understanding of the mechanism is at the forefront of devising high-performance OPTM devices.     

Degradation behavior of Ta2O5 stacks and its dependence on the gate electrode

Response of 8 nm Ta₂O₅ stacks with Al and Au gate electrodes to voltage stress at room temperature and at 100 °C is investigated. Stress-induced leakage current (SILC) reveals significant gate dependence and distinct difference to SILC in SiO₂. The mechanisms for SILC generation and stress degradation are discussed. Unlike SiO₂, pre-existing traps and positive charge build-up are recognized as a key factor for generation of SILC in Ta₂O₅ stacks.     

Memory characteristics of Al2O3/La2O3/Al2O3 multi-layer films with various blocking and tunnel oxide thicknesses

In order to investigate charge trap characteristics with various thicknesses of blocking and tunnel oxide for application to non-volatile memory devices, we fabricated 5 and 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ and 15 nm Al₂O₃/5 nm La₂O₃/5, 7.5, and 10 nm Al₂O₃ multi-stack films, respectively. The optimized structure was 15 nm Al₂O₃ blocking oxide/5 nm La₂O₃ trap layer/5 nm Al₂O₃ tunnel oxide film. The maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in program mode and at ?13 V for 100 ms in erase mode. At these program/erase conditions, the threshold voltage of the 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ film did not change for up to about 10⁴ cycles. Although the value of the memory window in this structure was not large, it is thought that a memory window of 1.12 V is acceptable in the flash memory devices due to a recently improved sense amplifier.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Structural and electrical properties of radio frequency magnetron sputtered tantalum oxide films: Influence of post-deposition annealing

The as-deposited and annealed radio frequency reactive magnetron sputtered tantalum oxide (Ta₂O₅) films were characterized by studying the chemical binding configuration, structural and electrical properties. X-ray photoelectron spectroscopy and X-ray diffraction analysis of the films elucidate that the film annealed at 673 K was stoichiometric with orthorhombic β-phase Ta₂O₅. The dielectric constant values of the tantalum oxide capacitors with the sandwich structure of Al/Ta₂O₅/Si were in the range from 14 to 26 depending on the post-deposition annealing temperature. The leakage current density was <20 nA cm^?2 at the gate bias voltage of 0.04 MV/cm for the annealed films. The electrical conduction mechanism observed in the films was Poole–Frenkel.     

Characterization and production metrology of gate dielectric films

We report efforts to develop optical dispersion models for new high k materials and silicon oxynitrides. We find the Tauc–Lorentz model provides superior fits to Ta₂O₅ and ZrO₂ dielectric films in the spectral range 1.5–6.0 eV. However, for typical oxynitrides which do not absorb below ∼6.0 eV, we find the Tauc–Lorentz model confers no advantage over models which do not account for absorption. For the oxynitrides, we also find a monotonic relationship between film refractive index and nitrogen concentration, potentially useful for gate dielectric process control.     

A study on the electrical characteristics of InGaZnO thin-film transistor with HfLaO gate dielectric annealed in different gases

The effects of dielectric-annealing gas (O₂, N₂ and NH₃) on the electrical characteristics of amorphous InGaZnO thin-film transistor with HfLaO gate dielectric are studied in-depth, and improvements in device performance by the dielectric annealing are observed for each gas. Among the samples, the N₂-annealed sample has a high saturation carrier mobility of 35.1 cm²/V s, the lowest subthreshold swing of 0.206 V/dec and a negligible hysteresis. On the contrary, the O₂-annealed sample shows poorer performance (e.g. saturation carrier mobility of 15.7 cm²/V s, larger threshold voltage, larger subthreshold swing of 0.231 V/dec and larger hysteresis), which is due to the decrease of electron concentration in InGaZnO associated with the filling of oxygen vacancies by oxygen atoms. Furthermore, the NH₃-annealed sample displays the lowest threshold voltage (1.95 V), which is attributed to the increased gate-oxide capacitance and introduced positive oxide charges. This sample also reveals a change in the dominant trap type due to the over-reduction of acceptor-like border and interface traps, as demonstrated by a hysteresis phenomenon in the opposite direction. Lastly, the low-frequency noise of the samples has also been studied to support the analysis based on their electrical characteristics.     

Amorphous ternary rare-earth gate oxides for future integration in MOSFETs

In this contribution we present results on the structural and electrical properties of amorphous REScO₃ (RE = La, Gd, Tb, Sm) and LaLuO₃ thin films. The study reveals that these oxides are potential candidates for so-called higher-k dielectrics for forthcoming MOSFET generations. High dielectric constants up to 32, low leakage currents and low interface trap densities are determined for amorphous thin films prepared by pulsed-laser deposition, molecular beam deposition and e-gun evaporation. Moreover, we show that LaLuO₃ gate stacks annealed up to 1050 °C maintain low leakage current densities without substantial EOT increase. Finally, promising results for n-MOSFETs with GdScO₃ as gate dielectric processed on strained silicon-on-insulator substrates are also shown.     

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (Zr_xSi_1−xO₂) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO₂ and ZrO₂ targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the Zr_xSi_1−xO₂ film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr_0.85Si_0.15O₂ dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μ_FE=51.7 cm²/Vs), and threshold voltage shift (ΔV_TH=0.03 V).     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

A study of the role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O2 based high density plasma for advanced DRAMs

The role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O₂ based high density plasma was studied. HBr/O₂-based polysilicon etch process used in this study seems to be highly selective to the underlying oxide and produce a dielectric fill-friendly post-etch profile depending on the flow rates of HBr and oxygen. When appropriate amounts of HBr and oxygen (∼30 sccm of HBr and ∼3 sccm of oxygen) are present in the etch plasma, brominated silicon oxide seems to be deposited on the original gate oxide and the gate stack sidewall from the reaction of SiBr_x (reaction product during polysilicon etch step) and oxygen during the HBr/O₂-based oxide etch process. The deposited brominated oxide on the thin gate oxide seems to make the HBr/O₂-based plasma etch process extremely selective to the thin gate oxide by protecting the underlying gate oxide. The deposited brominated oxide on the gate stack sidewall seems to prevent the notching by protecting the sidewall during gate stack etching. The etch rate of the brominated oxide seems to be much faster than that of the thermal oxide during the 200:1 diluted HF cleaning. However, the deposited brominated oxide on the thin gate oxide and the gate stack sidewall during the plasma etching survived the following 1 min 200:1 diluted HF cleaning, as was observed in a TEM micrograph (Fig. 2(a)).     

Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors

The present study analyzed the effects of the polar functional groups and rough topography of the gate dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al₂O₃ gate dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to <0.01 cm²/V s and was related to the many polar functional groups and the rough topography of the gate dielectric, which formed localized trap states in the band gap and created disorder in the crystal structure. In addition, the electric dipole of the polar groups and the fixed interface charges induced a positive shift of the threshold voltage and an increase in the off-state current. After aging of the oxygen plasma-treated gate dielectrics, the reduced number of polar groups led to greatly enhanced charge mobility, a less positive shift of the threshold voltage, a lower off-state current, and lower activation energy compared to layers without aging. However, the mobility still remained lower than for layers without plasma treatment owing to the rough topography of the gate dielectric.     

Low-voltage,high-performance n-channel organic thin-film transistors based on tantalum pentoxide insulator modified by polar polymers

Polar polymers (polyfluorene copolymers, PFN–PBT) with different polarities are utilized to modify the surface of tantalum pentoxide (Ta₂O₅) insulator in n-channel organic thin-film transistors (OTFTs). A high mobility of 0.55 cm²/Vs, high on/off current ratio of 1.7 × 10⁵, and low threshold voltage of 2.8 V are attained for the OTFT with the modification polymers, the performances of which are much better than those of OTFT with only Ta₂O₅ insulator. The performances of the OTFT with only Ta₂O₅ insulator are only 0.006 cm²/Vs in mobility, 5 × 10³ in on/off ratio, and 12.5 V in threshold voltage. Furthermore, it is found that the threshold voltage of the OTFTs with PFN–PBT modification layer is easily tuned by polarities of the polymers. Further studies show that self-assembly dipole moments in the polymers play an important role in the improvement of the OTFT performances.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

ZrO2 insulator modified by a thin Al2O3 film to enhance the performance of InGaZnO thin-film transistor

A high-performance InGaZnO (IGZO) thin-film transistor (TFT) with ZrO₂–Al₂O₃ bilayer gate insulator is fabricated. Compared to IGZO-TFT with ZrO₂ single gate insulator, its electrical characteristics are significantly improved, specifically, enhancement of I_on/I_off ratios by one order of magnitude, increase of the field-effect mobility (from 9.8 to 14 cm²/Vs), reduction of the subthreshold swing from 0.46 to 0.33 V/dec, the maximum density of surface states at the channel-insulator interface decreased from 4.3 × 10¹² to 2.5 × 10¹² cm⁻². The performance enhancements are attributed to the suppression of leakage current, smoother surface morphology, and suppression of charge trapping by using Al₂O₃ films to modify the high-k ZrO₂ dielectric.     

Composition,structure and electrical properties of DC reactive magnetron sputtered Al2O3 thin films

Thin films of alumina (Al₂O₃) were deposited over Si 〈1 0 0〉 substrates at room temperature at an oxygen gas pressure of 0.03 Pa and sputtering power of 60 W using DC reactive magnetron sputtering. The composition of the as-deposited film was analyzed by X-ray photoelectron spectroscopy and the O/Al atomic ratio was found to be 1.72. The films were then annealed in vacuum to 350, 550 and 750 °C and X-ray diffraction results revealed that both as-deposited and post deposition annealed films were amorphous. The surface morphology and topography of the films was studied using scanning electron microscopy and atomic force microscopy, respectively. A progressive decrease in the root mean square (RMS) roughness of the films from 1.53 nm to 0.7 nm was observed with increase in the annealing temperature. Al–Al₂O₃–Al thin film capacitors were then fabricated on p-type Si 〈1 0 0〉 substrate to study the effect of temperature and frequency on the dielectric property of the films and the results are discussed.