The transition from bipolaron to triplet-polaron magnetoresistance in a single layer organic semiconductor device

We measure the current–voltage–luminescence (I–V–L) and Magneto-Conductance (MC) response of a poly(3-hexyl-thiophene) (P3HT) based device (Au/P3HT(300 nm)/Al) in forward and reverse bias. In reverse bias (<1 V), the negative MC is described by a single non-Lorentzian function, consistent with the bipolaron theory. In forward bias, the transition from negative saturation MC (low bias) to positive saturation MC (high bias) occurs when the current density exceeds ∼10⁻² A cm⁻² and coincides with electroluminescence. Under these conditions the triplet density (∼10¹⁵ cm⁻³) becomes comparable to the hole density (∼10¹⁶ cm⁻³), consistent with the triplet-polaron interaction theory. From the current density dependence of the MC we conclude that in forward bias both mechanisms must be occurring simultaneously, within a given device, and that the overall sign of the MC results from competition between the two mechanisms.     

Solution-processed single-crystal perylene diimide transistors with high electron mobility

We have successfully demonstrated a single-crystal field-effect transistors (FETs) based on an asymmetric perylenetetracarboxylic diimide (a-PDI) compound with polystyrene (PS)/SiO₂ bilayer as gate dielectric. The single crystals are in-situ grown on substrate from simple solution evaporation method, thus may be suitable for large area electronics applications. The PS modified gate dielectric could minimize charge trapping by the hydroxyl groups of the SiO₂ surface. The resulting solution processed single crystals transistors are characterized in ambient air, and exhibited maximum electron mobility of ca. 1.2 cm² V⁻¹ s⁻¹ and high I_on:I_off > 10⁵.     

Determination of the laterally homogeneous barrier height of palladium Schottky barrier diodes on n-Ge (1 1 1)

We have studied the experimental linear relationship between barrier heights and ideality factors for palladium (Pd) on bulk-grown (1 1 1) Sb-doped n-type germanium (Ge) metal-semiconductor structures with a doping density of about 2.5×10¹⁵ cm^?3. The Pd Schottky contacts were fabricated by vacuum resistive evaporation. The electrical analysis of the contacts was investigated by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements at a temperature of 296 K. The effective barrier heights from I–V characteristics varied from 0.492 to 0.550 eV, the ideality factor n varied from 1.140 to 1.950, and from reverse bias capacitance–voltage (C^?2–V) characteristics the barrier height varied from 0.427 to 0.509 eV. The lateral homogenous barrier height value of 0.558 eV for the contacts was obtained from the linear relationship between experimental barrier heights and ideality factors. Furthermore the experimental barrier height distribution obtained from I–V and (C^?2?V) characteristics were fitted by Gaussian distribution function, and their mean values were found to be 0.529 and 0.463 eV, respectively.     

Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics

A bottom-gate/top-drain/source contact ZnO nanoparticle thin-film transistor was fabricated using a low temperature annealing process (150 °C) suitable for flexible electronics. Additionally, a high-k resin filled with TiO₂ nanoparticles was used as gate dielectric. After fabrication, the transistors presented almost no hysteresis in the I–V curve, a threshold voltage (V_T) of 2.2 V, a field-effect mobility on the order of 0.1 cm²/V s and an I_ON/I_OFF ratio of about 10⁴. However, the transistor is sensitive to aging effects due to interactions with the ambient air, resulting in current level reduction caused by trapped oxygen at the nanoparticle surface, and an anti-clockwise hysteresis in the transfer curve. It was demonstrated, conjointly, the possible desorption of oxygen by voltage stress and UV light exposure.     

The influence of high energy electron irradiation on the Schottky barrier height and the Richardson constant of Ni/4H-SiC Schottky diodes

The influence of high energy electron (HEE) irradiation from a Sr-90 radio-nuclide on n-type Ni/4H–SiC samples of doping density 7.1×10¹⁵ cm⁻³ has been investigated over the temperature range 40–300 K. Current–voltage (I–V), capacitance–voltage (C–V) and deep level transient spectroscopy (DLTS) were used to characterize the devices before and after irradiation at a fluence of 6×10¹⁴ electrons-cm⁻². For both devices, the I–V characteristics were well described by thermionic emission (TE) in the temperature range 120–300 K, but deviated from TE theory at temperature below 120 K. The current flowing through the interface at a bias of 2.0 V from pure thermionic emission to thermionic field emission within the depletion region with the free carrier concentrations of the devices decreased from 7.8×10¹⁵ to 6.8×10¹⁵ cm⁻³ after HEE irradiation. The modified Richardson constants were determined from the Gaussian distribution of the barrier height across the contact and found to be 133 and 163 A cm⁻² K⁻² for as-deposited and irradiated diodes, respectively. Three new defects with energies 0.22, 0.40 and 0.71 eV appeared after HEE irradiation. Richardson constants were significantly less than the theoretical value which was ascribed to a small active device area.     

Charge carrier mobility and lifetime of organic bulk heterojunctions analyzed by impedance spectroscopy

Charge carrier diffusion and recombination in an absorber blend of poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl C₆₁-butyric acid methyl ester (PCBM) with indium tin oxide (ITO) and aluminium contacts have been analyzed in the dark by means of impedance spectroscopy. Reverse bias capacitance exhibits Mott–Schottky-like behavior indicating the formation of a Schottky junction (band bending) at the P3H:PCBM-Al contact. Impedance measurements show that minority carrier (electrons) diffuse out of the P3HT:PCBM-Al depletion zone and their accumulation contributes to the capacitive response at forward bias. A diffusion–recombination impedance model accounting for the mobility and lifetime parameters is outlined. Electron mobility results to be 2 × 10⁻³ cm² V⁻¹ s⁻¹ and lifetime lies within the milliseconds timescale.     

Charge transport properties and microstructure of polythiophene/polyfluorene blends

We present a combined charge transport and X-ray diffraction study of blends based on regioregular poly(3-hexylthiophene) (P3HT) and the polyfluorene co-polymer poly((9,9-dioctylfluorene)-2,7-diyl-alt-[4,7-bis(3-hexylthien-5-yl)-2,1,3-benzothiadiazole]-2′,2′′-diyl) (F8TBT) that are used in efficient all-polymer solar cells. Hole mobility is observed to increase by nearly two orders of magnitude from less than 10^?7 cm² V^?1 s^?1 for as spin-coated blends to 6 × 10^?6 cm² V^?1 s^?1 for blends annealed at 453 K at a field of 2.7 × 10⁵ V/cm, but still significantly below the time-of-flight mobility of unblended P3HT of 1.7 × 10^?4 cm² V^?1 s^?1. The hole mobility of the blends also show a strong negative electric-field dependence, compared with a relatively flat electric-field dependence of unblended P3HT, suggestive of increased spatial disorder in the blends. X-ray diffraction measurements reveal that P3HT/F8TBT blends show a phase separation of the two components with a crystalline part attributed to P3HT and an amorphous part attributed to F8TBT. In as-spun and mildly annealed blends, the measured d-values and relative intensities of the 100, 200 and 300 P3HT peaks are noticeably different to unblended P3HT indicating an incorporation of F8TBT in P3HT crystallites that distorts the crystal structure. At higher anneal temperatures the blend d-values approach that of unblended P3HT suggesting a well separated blend with pure P3HT crystallites. P3HT crystallite size in the blend is also observed to increase with annealing from 3.3 to 6.1 nm, however similar changes in crystallite size are observed in unblended P3HT films with annealing. The lower mobility of P3HT/F8TBT blends is attributed not only to increased P3HT structural disorder in the blend, but also due to the blend morphology (increased spatial disorder). Changes in hole mobility with annealing are interpreted in terms of the need to form percolation networks of P3HT crystallites within an F8TBT matrix, with a possible contribution due to the intercalation of F8TBT in P3HT crystallites acting as defects in the as-prepared state.     

Current–voltage and capacitance–voltage characteristics of Al Schottky contacts to strained Si-on-insulator in the wide temperature range

The electrical characteristics of Al/strained Si-on-insulator (sSOI) Schottky diode have been investigated using current–voltage (I–V) and capacitance–voltage (C–V) measurements in the wide temperature range of 200–400 K in steps of 25 K. It was found that the barrier height (0.57–0.80 eV) calculated from the I–V characteristics increased and the ideality factor (1.97–1.28) decreased with increasing temperature. The barrier heights determined from the C–V measurements were higher than those extracted from the I–V measurements, associated with the formation of an inhomogeneous Schottky barrier at the interface. The series resistance estimated from the forward I–V characteristics using Cheung and Norde methods decreased with increasing temperature, implying its strong temperature dependence. The observed variation in barrier height and ideality factor could be attributed to the inhomogeneities in Schottky barrier, explained by assuming Gaussian distribution of barrier heights. The temperature-dependent I–V characteristics showed a double Gaussian distribution with mean barrier heights of 0.83 and 1.19 eV and standard deviations of 0.10 and 0.16 eV at 200–275 and 300–400 K, respectively. From the modified Richardson plot, the modified Richardson constant were calculated to be 21.8 and 29.4 A cm⁻² K⁻² at 200–275 and 300–400 K, respectively, which were comparable to the theoretical value for p-type sSOI (31.6 A cm⁻² K⁻²).     

Hybrid dual gate ferroelectric memory for multilevel information storage

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200 °C), and demonstrate excellent performance with high hole mobility of 2.7 cm² V⁻¹ s⁻¹, large memory window of ∼18 V, and a low sub-threshold swing ∼−4 V dec⁻¹. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.     

ZrO2 insulator modified by a thin Al2O3 film to enhance the performance of InGaZnO thin-film transistor

A high-performance InGaZnO (IGZO) thin-film transistor (TFT) with ZrO₂–Al₂O₃ bilayer gate insulator is fabricated. Compared to IGZO-TFT with ZrO₂ single gate insulator, its electrical characteristics are significantly improved, specifically, enhancement of I_on/I_off ratios by one order of magnitude, increase of the field-effect mobility (from 9.8 to 14 cm²/Vs), reduction of the subthreshold swing from 0.46 to 0.33 V/dec, the maximum density of surface states at the channel-insulator interface decreased from 4.3 × 10¹² to 2.5 × 10¹² cm⁻². The performance enhancements are attributed to the suppression of leakage current, smoother surface morphology, and suppression of charge trapping by using Al₂O₃ films to modify the high-k ZrO₂ dielectric.     

The effects of thermal annealing on the electrical characteristics of Au/n–InP/In diode

An Au/n–InP/In diode has been fabricated in the laboratory conditions and the current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the diode have been measured in room temperature. In order to observe the effect of the thermal annealing, this diode has been annealed at temperatures 100 and 200 °C for 3 min in N₂ atmosphere. The characteristic parameters such as leakage current, barrier height and ideality factor of this diode have been calculated from the forward bias I–V and reverse bias C–V characteristics as a function of annealing temperature. Also the rectifying ratio of the diode is evaluated for as-deposited and annealed diode.     

The effect of external stress on the electrical characteristics of AlGaN/GaN HEMTs

The electrical characteristics of AlGaN/GaN high electron mobility transistors under the application of uniform in-plane tensile and compressive stress were measured. The results demonstrate the change of the drain–source I_ds–V_ds characteristics as a function of the external stress. The output current at V_ds = 10 V increases linearly with the stress with the slope about 3 × 10⁻⁶ A MPa⁻¹. It is associated with the piezoelectric effect and kink effect. Moreover, the magnitude of the kink effect is found to be affected by the stress. It displays a linear changing trend with the slope of 3.3 × 10⁻⁴ mS MPa⁻¹ within the stress level. The energy band structure is suggested to be responsible for the dependence of the kink effect on the stress.     

Effects of semiconductor/dielectric interfacial properties on the electrical performance of top-gate organic transistors

We investigated the effects of varying the properties of the interface between a semiconductor P3HT layer and a dielectric Cytop™ layer on the performances of the resulting transistor devices by comparing the mobilities of devices prepared with bottom gate/bottom contact or top gate/bottom contact architectures. The reduced channel roughness that arose from the thermal annealing step dramatically enhanced the field-effect mobility, yielding the highest mobility yet obtained for a top-gate transistor: 0.12 cm²/V s. High-performance OFETs may be fabricated by controlling the channel roughness and the properties of the interface between the semiconductor and the gate dielectric.     

Electrical and photovoltaic properties of SnSe/Si heterojunction

Thin film of SnSe is deposited on n-Si single crystal to fabricate a p-SnSe/n-Si heterojunction photovoltaic cell. Electrical and photoelectrical properties have been studied by the current density–voltage (J–V) and capacitance–voltage (C–V) measurements at different temperatures. The fabricated cell exhibited rectifying characteristics with a rectification ratio of 131 at ±1 V. At low voltages (V<0.55 V), the dark forward current density is controlled by the multi-step tunneling mechanism. While at a relatively high voltage (V>0.55 V), a space charge-limited-conduction mechanism is observed with trap concentration of 2.3×10²¹ cm⁻³. The C–V measurements showed that the junction is of abrupt nature with built-in voltage of 0.62 V which decreases with temperature by a gradient of 2.83×10⁻³ V/K. The cell also exhibited strong photovoltaic characteristics with an open-circuit voltage of 425 mV, a short-circuit current density of 17.23 mA cm⁻² and a power conversion efficiency of 6.44%. These parameters have been estimated at room temperature and under light illumination provided by a halogen lamp with an input power density of 50 mW cm⁻².     

Improving solution-processed n-type organic field-effect transistors by transfer-printed metal/semiconductor and semiconductor/semiconductor heterojunctions

Solution-processed n-type organic field effect transistors (OFETs) are in need of proper metal contact for improving injection and mobility, as well as balanced hole mobility for building logic circuit units. We address the two distinct problems by a simple technique of transfer-printing. Transfer-printed Au contacts on a terrylene-based semiconductor (TDI) significantly reduced the inverse subthreshold slope by 5.6 V/dec and enhanced the linear mobility by over 5 times compared to evaporated Au contacts. Hence, devices with a high-work-function metal (Au) are comparable with those with low-work-function metals (Al and Ca), indicating a fundamental advantage of transfer-printed electrodes in electron injection. We also transfer-printed a poly(3-hexylthiophene) (P3HT) layer onto TDI to construct a double-channel ambipolar transistor by a solution process for the first time. The transistor exhibits balanced hole and electron mobility (3.0 × 10⁻³ and 2.8 × 10⁻³ cm² V⁻¹ s⁻¹) even in a coplanar structure with symmetric Au electrodes. The technique is especially useful for reaching intrinsic mobility of new materials, and enables significant enlargement of the material tanks for solution-processed functional heterojunction OFETs.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Raman characterization and electrical properties of poly(3-hexylthiophene) doped electrochemically in an ionic liquid-gated transistor geometry

Using Raman spectroscopy, we observed carriers, polarons and bipolarons formed in an ionic-liquid-gated P3HT electrochemical transistor with an ionic liquid [BMIM][TFSI] as a gate dielectric. The relationships between the source−drain current (I_D), the gate voltage (V_G) at a constant source−drain voltage (V_D), and injected charges at each V_G were investigated. An increase in I_D is attributed to the formation of positive polarons, whereas a decrease in I_D corresponded to positive bipolarons. Thus, positive polarons are efficient carriers in P3HT electrochemical transistors. Charge densities, doping levels, electrical conductivities, and mobilities of polarons in P3HT were calculated from the electrochemical measurements. Only positive polarons exist below the dopant level x = 27 mol%, whereas at higher doping levels, polarons and bipolarons coexist. The mobility of polarons was dependent on the doping level. The highest mobility was 0.31 cm² V⁻¹ s⁻¹ at x = 15 mol%.     

Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature

In this paper, we have investigated the electrical characteristics of power lateral double-diffused MOSFETs (LDMOSFETs) having different gate lengths (2.1–3 μm) and drift lengths (6.6–12.6 μm) in the temperature range 100–500 K. The results of this study indicate that gate length and drift region length have a great effect on electrical characteristics, but they have little effect on temperature dependence. The specific on-resistance and the off-state breakdown voltage increase with temperature. The result shows that the specific on-resistance increases exponentially with the exponent 2.2 and, by contrast, the off-state breakdown voltage increases linearly with a slope of 100 mV/K (drift region concentration of measured device: 2×10¹⁵ cm⁻³). As a result, R_on/BV, known for a figure of merit of power device, increases with temperature.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Investigation of deep level defects in copper irradiated bipolar junction transistor

Commercial bipolar junction transistor (2N 2219A, npn) irradiated with 150 MeV Cu¹¹⁺-ions with fluence of the order 10¹² ions cm^?2, is studied for radiation induced gain degradation and deep level defects. I–V measurements are made to study the gain degradation as a function of ion fluence. The properties such as activation energy, trap concentration and capture cross-section of deep levels are studied by deep level transient spectroscopy (DLTS). Minority carrier trap levels with energies ranging from E_C ? 0.164 eV to E_C ? 0.695 eV are observed in the base–collector junction of the transistor. Majority carrier trap levels are also observed with energies ranging from E_V + 0.203 eV to E_V + 0.526 eV. The irradiated transistor is subjected to isothermal and isochronal annealing. The defects are seen to anneal above 350 °C. The defects generated in the base region of the transistor by displacement damage appear to be responsible for transistor gain degradation.