Counting of deep-level traps using a charge-coupled device

Quantization in dark current generation has been observed for the first time through the use of a virtual-phase charge-coupled device. Two sites for bulk silicon dark current have been identified with capture cross sections of 1.8 × 10^-15cm²and 5.4 × 10^-16cm², and concentrations of 1.3 × 10⁹cm^-3and 1.5 × 10⁸cm^-3, respectively.     

Some reactive effects in forward biased junctions

The small-signal equivalent parallel capacity of forward-biased semiconductor junctions is strongly dependent on the current. At very low currents (less than 10 µa for a junction area of 1 mm²) the capacity appears to be chiefly due to space charge effects. For currents up to approximately 100 µa, the capacity complies with Shockley's predicted low-level theory. For larger currents, however, there is a definite deviation from the low-level diffusion predominance and capacity reaches a maximum after which it decreases through zero and then goes to large inductive values. The latter phenomena is explained, qualitatively, by considering an inductance in series with the diffusion capacity. The capacity increases linearly with current but the inductance (due to conductivity modulation) increases faster. The result is that a change from an equivalent RC circuit to an equivalent RL circuit is made at high enough currents (5 ma is a typical value for the 1 mm²junction area). Measurements were made on abrupt silicon junction diodes with junction areas of about 7 × 10^-4, 10^-2, 10^-1cm²and on the emitter junction (about 5 × 10^-5cm²) of a diffused base silicon transistor.     

Large-signal analysis of Lo-Hi-Lo double-drift silicon IMPATT diodes at 50 GHz

Large-signal analysis of a lo-hi-lo double-drift silicon IMPATT diode at 50 GHz shows that the device is capable of output power of 1.1 W and efficiency of 20 percent for a device area of 2 × 10^-5cm²at a dc biasing current density of 12 kA/cm²and ac voltage amplitude of 12 V. It is also found that, both output power values and efficiencies decrease with increasing enhanced leakage current.     

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration Noffin offset-gate regions. Leakage current markedly decreases from 1 × 10^-9to 2 × 10^-11A at VD= 10 V as Noffis varied from 1 × 10¹⁸to 1 × 10¹⁷cm^-3. A maximum ON/OFF current ratio of 10⁸is obtained at 1 × 10¹⁷cm^-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.     

Measurement of electron attachment processes in a high-temperature plasma

An experimental technique has been developed for measuring rate constants of electron attaching reactions as well as ion-molecule reactions in plasma at 2000-3000°K. Reaction product ions are mass analyzed and rate constants are obtained from plots of the collected ion current. The rate constant for O^-formation from N2O varies from about 3 to 9×10^-9cm³/s over the temperature range of 2400-3000°K while the rate constant for F^-formation from SF6varies from 2.8 to 4×10^-10cm³/s for temperatures from 2775 to 3000°K. A brief survey of experimental techniques for measuring electron attachment rate constants at lower temperatures is also given, together with a comparison of these rate constants and present high-temperature values.     

Ultrasmall superconducting tunnel junctions

Extremely small-area superconducting Josephson junctions have been fabricated using a newly developed electron-beam lithography technique. The junctions are composed of Pb-In base electrodes and Pb counter electrodes. Areas of the junctions range from 1 to 3 × 10^-10cm². The estimated capacitance is ∼10^-15F. Junctions have been produced with resistances of ∼100 Ω which have ∼20-percent hysteresis in the critical current at a temperature of 4 K.     

Fast determination of the effective channel length and the gate Oxide thickness in polycrystalline Silicon MOSFET's

MOSFET's with variable channel lengths have been fabricated in both mono- and fine-grained polycrystalline silicon. We present a new method based upon a simple CV technique, to measure the effective channel length and gate oxide thickness. The channel-length reduction of the poly-Si MOSFET's was about 7.8 µm from which an effective lateral diffusion coefficient at 1000°C of phosphorus of 5 × 10^-13cm²/s was calculated. The electron mobility was in the range of 10-20 cm²/V.s and the threshold voltage was about 17 V. The MOSFET's in mono-Si have been used as a reference. The results of measurements on these devices are in agreement with literature.     

Elimination of the guard ring in uniform avalanche photodiodes

A conventionalp^{+}-n(orn^{+}-p) planar avalanche photodiode with a 10^-4cm²active area has ∼2.5 × 10^-4cm²total area because of its protecting guard ring and has a series resistance of ∼50 to 100 ohms. For narrow-band applications, multiplications greater than 10 are necessary to equal the available output power of a conventional nonavalanchingp-i-nphotodiode. In broad-band applications, significant multiplications are necessary to compete favorably with thep-i-nwhen the active area is less than 10^-4cm²or when the signal frequency is > 1 GHz. Ap-n^{+}planar structure is discussed that eliminates the need for a guard ring because positive junction curvature occurs on the high-resistivity side. Thep-n^{+}diodes can be designed to have resistances (Rs∼2 ohms), capacitances (C < 1 pf), and RC cutoff frequencies (fco>100 GHz) equivalent to those of thep-i-nand to have uniform multiplication as well. Closer array spacings can be achieved than with the guard ring structure, as well as higher effective quantum efficiencies in the avalanche mode. Practical realization of thep-n^{+}structure has been achieved in silicon by a combination of epitaxial and doped-oxide processing. Seven-mil-diameter junctions with high breakdown voltage (110 V) and uniform avalanche properties have been constructed.     

Integral heat-sink IMPATT diodes fabricated using p+etch stop

The problems in batch fabrication of integral heat-sink IMPATT diodes are greatly simplified through a newly developed preferential etching technique. Devices fabricated utilizing the new technique have thermal resistance (θjc) values of 17-20°C/W for an active area of 2 × 10^-4cm².     

A 64K SRAM with high immunity from heavy ion induced latch-up

A 64-kbit SRAM with high latch-up immunity has been developed with the application of a well-source structure combined with an epi-substrate. Heavy-ion beam exposure tests reveal that the device has high immunity from cosmic-ray induced latch-up, and the soft-error cross section is about 8.6 × 10^-7cm²/(bit particle) for 73-MeV Ar ions.     

Laser-recrystallized polycrystalline-silicon thin-film transistors with low leakage current and high switching ratio

Laser-recrystallized polycrystalline-silicon thin-film transistors (poly-Si TFT's) with offset-gate structures have been fabricated on quartz substrates. Offset-gate structures make it possible to reduce leakage currents to as low as 5 × 10^-14A/µm at VD= 10 V, more than two orders of magnitude lower than that in conventional-structure poly-Si TFT's. Optimization of the dopant concentration in offset-gate regions minimizes degradation of drive current, enabling high switching ratios exceeding 10⁸. Calculations based on the quasi-two-dimensional model indicate that the reduction in leakage current is due to a decrease in lateral electric field strength in the drain depletion region.     

Efficiency of the a-Si:H solar cell and grain size of SnO2transparent conductive film

The relationship between average grain size on the surface of SnO2transparent conductive film and conversion efficiency of the a-Si:H solar cell was investigated. a-Si:H solar cells were fabricated on SnO2/glass substrates with various grain sizes. The cell structure was glass/p(SiC)-i-n/Al and the effective cell area was 4 × 10^-2cm². The reflectivity from the glass substrate was reduced to about 7 percent with increasing the grain size from 0.1 to 0.8µm, and the short-circuit current was inceased from 12 to 14mA/cm². A 7.9 percent of conversion efficiency was achieved using milky SnO2film of 0.4-µm average grain size at AM-100mW/cm².     

Diamond cold cathode

Diamond cold cathodes have been formed by fabricating mesa-etched diodes using carbon ion implantation into p-type diamond substrates. When these diodes are forward biased, current is emitted into vacuum. The cathode efficiency (emitted current divided by diode current) varies from 2×10^-4 to 1×10^-10 and increases with the addition of 10^-2-torr partial pressure of O₂ into the vacuum system. Current densities of 0.1 to 1 A-cm^-2 are estimated for a diode current of 10 mA. This compares favorably with Si cold cathodes (not coated with Cs), which have efficiencies of ~2×10^-5 and current densities of ~2×10^-2 A-cm^-2. It is believed that higher current densities and efficiencies can be obtained with more efficient cathode designs and an ultrahigh-vacuum environment     

A method of determining impurity diffusion coefficients and surface concentrations of drift transistors

In order to control the electrical parameters of drift transistors, it was found necessary to control the impurity concentration gradient in the base. An extension of the space charge widening theory provides a method of calculating this gradient, the surface concentration, and the diffusion coefficient. By this method, the diffusion coefficient of arsenic into germanium at 725°C was found to be 3.1 × 10^-12cm²/second and the initial surface concentration was of the order of 10²⁰atoms/cm³. Universal graphs for design calculations and rapid reference are presented.     

DC characteristics of high-breakdown-voltage p-i-n diodes made by20-MeV Si implantation in InP:Fe

A vertical p-i-n diode is made for the first time in InP:Fe using megaelectronvolt energy ion implantation, A 20-MeV Si implantation and kiloelectronvolt energy Be/P coimplantation are used to obtain a buried n⁺ layer and a shallow p⁺ layer, respectively. The junction area of the device is 2.3×10^-5 cm² and the intrinsic region thickness is ≈3 μm. The device has a high breakdown voltage of 110 V, reverse leakage current of 0.1 mA/cm² at -80 V, off-state capacitance of 2.2 nF/cm² at -20 V, and a DC incremental forward resistance of 4 Ω at 40 mA     

High current p/p+-diamond Schottky diode

Epitaxial p-type Schottky diodes have been fabricated on p⁺ -substrate. While the activation energy of the epitaxial layer conductivity is 390 meV, that of the substrate is only 50 meV. At forward bias the substrate conductivity dominates above 150°C, leading for a 5×10^-5 cm² area contact to a series resistance of 14 Ω at 150°C reducing to 8 Ω at 500°C. To our knowledge, this is the lowest series resistance reported so far for a diamond Schottky diode enabling extremely high current densities of 10³ A/cm and a current rectification ratio at ±2 V of 10⁵ making these diodes already attractive as high temperature rectifiers     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.     

On oxide—nitride interface traps by thermal oxidation of thin nitride in metal-oxide-nitride-oxide-semiconductor memory structures

Charging properties of metal-oxide(top-oxide)-nitride-oxide (tunnel-oxide)-semiconductor (MONOS) memory structures characterized by very low program voltage have been investigated and analyzed. By comparing the experimental observations with theoretical calculations, the capture cross section of the electron traps generated at the top oxide-nitride interface by thermal oxidation of the thin nitride primarily effecting the memory action of the MONOS devices is estimated to be about 6 × 10^-14cm².     

A new method of growing GaP crystals for light-emitting diodes

A method named synthesis, solute diffusion (SSD) has been developed for growing compound semiconductor crystals, GaP in particular, for light-emitting diode (LED) use. The grown crystal is cylindrically shaped and is composed of fairly large-size grains. Growth rate is limited by the diffusion process of phosphorus in the gallium melt. The diffusion coefficient was obtained from the growth rate and found to be 8×10^-5cm²s^-1at 1100°C with an activation energy of 0.65 eV. Donor impurities, tellurium or sulfur, can be reproducibly incorporated from 3×10¹⁷to 4×10¹⁸cm^-3, with segregation coefficients at 1150°C, 0.038 and 1.0, respectively. The quality of the grown crystals was observed to be exceptionally good, and the saucer-type pits were hardly observable in the crystal on modified AB etching. Highly efficient red-light-emitting junctions were reproducibly grown by only one single-layer-single-liquid-epitaxy process, in which zinc was doped from the vapor phase. A double-layer-single-epitaxy process, which we call "liquid epitaxial grown-in junction" process, was also developed and it produced highly efficient green LED's. The LED's grown on the SSD wafers have efficiencies up to 7.4 percent for red and 0.15 percent for green.