A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering

An oversampling bandpass digital-to-analog converter has been designed so as to eliminate the carrier leak and in-band SNR degradation that accompany I and Q channel mismatch in wireless transmitters. The converter combines a cascaded noise-shaping sigma-delta (/spl Sigma//spl Delta/) modulator with digital finite impulse response (FIR) and mixed-signal semi-digital filters that attenuate out-of-band quantization noise. The performance of the converter in the presence of current source mismatch has been improved through the use of bandpass data weighted averaging. An experimental prototype of the converter, integrated in a 0.25-/spl mu/m CMOS technology, provides 83 dB of dynamic range for a 6.25-MHz signal band centered at 50 MHz, and suppresses out-of-band quantization noise by 38 dB.     

An interpolative bandpass converter on a 1.2-μm BiCMOSanalog/digital array

The architecture and performance of an interpolative bandpass A/D converter (ADC) and digital quadrature demodulator dedicated for digital narrowband transmission systems, like the cellular radio mobile receiver, are presented. A prototype version has been implemented on a 1.2-μm/7-GHz BiCMOS analog/digital array. A bandpass signal centered at 6.5 MHz with 200-kHz bandwidth is demodulated and converted with a 55-dB signal-to-noise ratio giving 9-b performance     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

An 81-MHz IF receiver in CMOS

An 81-MHz CMOS IF receiver for digital wireless applications is presented. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage, and a sixth-order bandpass ΣΔ A/D converter. Incorporating 24 dB of programmable gain, the receiver achieves 92 dB of dynamic range in a 200 kHz bandwidth. Due to its IF sampling nature, the reciever is immune to de offset, flicker noise, and errors due to mismatches between I and Q signal paths. By utilizing a pseudo two-path resonator architecture in the bandpass ΣΔ A/D converter, a stable passband center frequency which is immune to capacitor mismatch is achieved. Implemented in 0.8-μm CMOS, this chip uses a single 3 V supply and consumes 14.4 mW of power     

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

Parallel Continuous-Time $DeltaSigma$ ADC for OFDM UWB Receivers

A parallel multibit continuous-time (CT) $DeltaSigma$ analog-to-digital converter for an orthogonal-frequency-division-multiplexing (OFDM) ultrawideband receiver intended to operate according to the IEEE 802.15.3a or the ECMA 368 (ISO/IEC 26907) standards has been designed. The overall CT $DeltaSigma$ converter consists of two modulators covering two unequal subbands (low-pass (LP) and bandpass (BP) subbands) that are arranged to operate in parallel and whose respective noise transfer functions (NTFs) are designed to match its corresponding frequency band. The composite NTF for the overall converter is defined as the minimum gain value out of these two individual NTFs. The LP and BP subbands were designed by using third- and fourth-order modulators, respectively, based on a 3-bit quantizer and operating at a clock frequency of 1056 MHz. NTF zero locations were optimized according to the criterion that all the in-band composite NTF gain maxima have approximately the same value. Combining OFDM signal characteristics and converter parameters, the effect of the quantization noise on the overall converter performance has been analytically derived. A simulation program has been realized to verify the performance of the converter.      

Digital detection of instability of higher order bandpasssigma-delta converters

A digital method of stabilising higher order sigma-delta converters is presented. Results are given for a third order bandpass ΣΔ converter with three continuous time LC filters tuned to 1/4 of clock frequency f_c     

A double Nyquist digital product detector for quadrature sampling

A technique for digitally obtaining the in-phase (I) and quadrature (Q) components of an IF signal is presented. Initially, the input bandpass signal is mixed to a carrier frequency that is one-fourth of the sampling rate of a single A/D converter. The digitized bandpass signal is converted into its I and Q components at one-half the A/D sample rate by a digital product detector (DPD) composed of a commutator, two sign alternators, and two FIR fractional-phase interpolator filters. This simple structure can yield image performance that is limited by A/D quantization using relatively low interpolator filter orders and IF bandwidths as large as one-half the sampling rate of the A/D converter. The DPD performs Nyquist limit demodulation of the sampled bandpass signal and, therefore, requires a minimal sampling rate. The theory of operation, an analytic proof, design methodology, and simulated performance results are presented. Simulated results show that -86 dB images can be obtained with 8-tap FIR interpolators and a 12 bit A/D converter. A VLSI implementation is also presented     

A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz     

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital ΣΔ modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.     

A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth

An integrated low-noise amplifier, mixer, bandpass /spl Delta//spl Sigma/ analog-to-digital converter (ADC), decimation filter, and two synthesizers implement a general-purpose back-end for a narrow-band superheterodyne receiver. The /spl Delta//spl Sigma/ ADC is merged with the mixer and combines LC, active-RC, and switched-capacitor resonators to achieve low noise and robust operation with low power consumption. A variable full-scale feature adds an automatic-gain-control capability to the ADC while saving power and minimizing noise at low signal levels.     

1 V power supply, low-power consumption A/D conversion techniquewith swing-suppression noise shaping

A 1 V power supply and low-power consumption A/D conversion technique using swing-suppression noise shaping is proposed. This technique makes it possible to power the on chip A/D converter in digital LSI's directly by a one-cell battery, without a dc-dc converter. Experimental results indicated good performance for the RF-to-baseband analog interface of a digital cordless phone. The A/D converter, fabricated with a 0.5 μm CMOS process, operates on a 1 V power supply, has a 10 bit dynamic-range with a 384 ksps sampling speed and consumes only 1.56 mW     

A reconfigurable low-pass/high-pass \varDelta \varSigma ADC suited for a zero-IF/low-IF receiver

This paper presents the design of a reconfigurable delta sigma analog to digital converter. Its main degree of freedom is the choice of the noise shaping between low-pass and high-pass. Thanks to this reconfiguration parameter, the converter takes full advantage of both noise shapings and employs the most suited architecture depending on the received standard. Moreover, the low-pass/high-pass reconfiguration makes the analog-to-digital converter compliant for both the low-IF and the zero-IF receiver architectures. The paper also presents a novel reconfigurable dynamic element matching technique which efficiently addresses the digital to analog converter mismatch for both the high-pass and the low-pass delta sigma modulators. The sampling frequency and the quantizer number of bits are likewise adjustable. A GSM/UMTS compliant delta sigma analog to digital converter including reconfigurable decimator has been designed in a 1.2 V 65 nm CMOS process. The high-pass modulator is employed in a low-IF receiver for the GSM mode to profit from its robustness against offset and 1/f noise. For the UMTS mode, the low-pass modulator is employed in a zero-IF receiver because of its lower sensitivity to clock jitter.     

A CMOS oversampling D/A converter with a current-mode semidigitalreconstruction filter

Oversampling digital-to-analog (D/A) converters employing sigma-delta modulation noise shaping and single-bit quantization are attractive for use in digital audio applications because of their relaxed reconstruction filtering requirements and their tolerance of component mismatch. However, the use of a two-level D/A interface results in a large amount of out-of-band quantization noise that typically must be attenuated by a carefully designed analog reconstruction filter. This paper introduces a means of simplifying the reconstruction filter design through the use of a semidigital finite-impulse-response (FIR) filter. In particular, it describes an oversampling D/A converter wherein a current-mode semidigital reconstruction filter is used to implement a multilevel D/A interface that attenuates the out-of-band quantization noise without requiring precise component matching. An experimental implementation of the converter achieves a dynamic range of 94 dB and 72 dB attenuation of out-of-band quantization noise for a baseband of 20 kHz. The prototype converter, which consists of a linear interpolator, a second-order noise shaper, and a 128-tap semidigital FIR filter, dissipates 59 mW from a 5-V supply and occupies an active area of 3 mm² when integrated in a 1.2-μm digital CMOS technology     

Impact of noise of linearity of SQUID feedback loops at high slewrate

A simplified digital DC SQUID (superconducting quantum interference device) system has been simulated to determine the degree of linearity in a digital flux-locked-loop (FLL), with 12-b D/A converter. The influence of comparator noise and quantization noise on the feedback loops corresponding to single- and two-pole integrators is investigated as a function of the normalized slew rate s_N =s/s_max. A simple approximation describing the attainable linearity up to a specific slew rate range is suggested. Measurements with and without a DC SQUID magnetometer in a digital FLL system yielded a satisfying agreement with simulations in the range 0.3<s_n⩽1     

An Injection-Locked Frequency-Tracking Σ∆ Direct Digital Frequency Synthesizer

A bandpass (BP) sigma-delta modulator (SigmaDeltaM)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BPSigmaDeltaM, shaping quantization noise out of the signal band. The single-bit BPSigmaDeltaM is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BPSigmaDeltaM out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BPSigmaDeltaM-based synthesizer is fabricated in a 0.25-mum digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than -105 dBc/Hz at a 10-kHz offset is achieved     

8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-digital converter (ADC) has been developed. A gain amplifier, a 14-b successive approximation ADC (SA-ADC), and a new column digital processor are employed in each column. The SA-ADC has sufficient operation speed to convert the pixel reset and the pixel signal into digital data in a row operation cycle. The column digital processor receives bit serial data from the SA-ADC output and performs subtraction of the reset data from the signal data in order to reduce column fixed pattern noise (FPN). Column FPN is successfully reduced to 0.36 e_rms ^- by this digital-domain column FPN correction. Low-voltage low-power serial video interface and noise decoupling on pixel drive voltages contribute to row-temporal-noise reduction to 0.31 e_rms ^-. Both column FPN and row temporal noise are not visible in spite of a low readout noise floor of 2.8 e_rms ^-.     

The Effect of a Bandpass Nonlinearity on Signal Detectability

When an angle-modulated signal plus noise constitute the input to a bandpass device exhibiting a nonlinear input-output power characteristic and AM to PM conversion, the noise component of the output has altered first- and second-order statistics. A method of evaluating the two-dimensional first-order statistics of this noise is presented. The effect on signal detectability of a nonlinearity inserted between two channel noise sources is studied; expressions for the mean square received phase error and probability of error (for coherent digital phase modulation) are derived. The hard limiting satellite channel, with Gaussian noise on the up and down links, is examined in detail, and it is demonstrated that the limiter can significantly affect signal detectability.     

An oversampled multibit CMOS D/A converter for digital audio with115-dB dynamic range

The analog part of a current-mode CMOS 5-b bidirectional digital/analog (D/A) converter for digital audio with 115-dB dynamic range and -90-dB distortion at 128-times oversampling is presented. The application of a multibit noise shaping approach combined with a sign-magnitude decoding in an oversampled D/A converter not only increases the dynamic range of the converter but also reduces the intermodulation sensitivity. A dynamic self-calibration technique is used to obtain the required relative accuracy and absolute linearity of the current sources. No laser or external trimming techniques are required