Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays

An analytical design methodology for continuous-time (CT) bandpass (BP) /spl Sigma//spl Delta/ modulators is presented. Second- and fourth-order tunable continuous time BP /spl Sigma//spl Delta/ modulator design equations are presented. A novel /spl Sigma//spl Delta/ loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the methodology is confirmed by mixed-signal behavioral simulations.     

Exact design of continuous-time sigma-delta modulators with multiple feedback DACs

A technique for the exact design of the noise transfer function of Continuous-Time (CT) Sigma-Delta modulators with arbitrary and multiple DAC responses and real op-amps is here presented. The approach, that presupposes linear behavior of active blocks, produces a CT modulator with the same noise shaping as its Discrete-Time counterpart. The method operates entirely in the time domain and accounts for non-idealities of real implementations such as finite gain and bandwidth of integrators. The procedure can be effectively implemented with circuit simulators to allow the exact design with transistor level blocks. A design example on a third-order scheme confirms the effectiveness of the method.     

On the implementation of input-feedforward delta-sigma modulators

This brief addresses some practical issues on the implementation of the input-feedforward delta-sigma modulators. First, the timing constraint imposed by the input-feedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed.     

A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators

Excess loop delay is one of the most critical non-idealities of continuous-time delta–sigma modulators as it leads to degradation of the signal-to-noise-ratio or even instability. A comprehensive study of the impact of excess loop delay on tunable continuous-time bandpass delta–sigma modulators using RC-resonators is performed in this paper, both analytically and by simulations. Moreover, a detailed analysis of the conventional compensation techniques for single-band continuous-time bandpass modulators as well as their adaptability to tunable bandpass modulators is performed. The results indicate that only tuning of the scaling coefficients is suitable to compensate for excess loop delay in high-speed tunable bandpass modulators. Based on this result, an approach to the compensation of excess loop delay is proposed which maps the poles of the noise transfer function (NFT) to almost ideal and thus stable positions. Excess loop delay equal to one clock cycle may thus be compensated while the available tuning range of the center frequency depends on the order and the out-of-band-gain of the NFT. A prototype implemented on a printed circuit board proves the feasibility of the proposed approach.     

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.     

A 1-GHz, multibit, continuous-time, delta-sigma ADC for Gigabit Ethernet

In this work the design of a continuous-time ΔΣ modulator for Gigabit Ethernet applications is presented. The input bandwidth and oversampling ratio are, respectively, 62.5 MHz and 8, resulting in a clock frequency of 1 GHz. It was designed and implemented in a standard 90 nm CMOS technology. The active area of the modulator measures . It consists of a loop filter based on RC-opamp integrators and a 3-bit quantizer which includes a data weighted averaging scrambler. A digital tuning scheme to deal with process variations has also been included. System level simulations including several non-ideal effects have been carried out in order to determine in detail the performance of the converter. Experimental results show a resolution of 7.1 effective bits, and a power consumption of 10.8 mW from a nominal power supply of 1 V.     

The design of high-order bandpass sigma-delta modulators using low-spread single-stage structure

A structure for single-stage high-order bandpass sigma-delta modulators (BPSDMs) is presented. The proposed structure introduces an additional internal path in each resonator, thus, adding one degree of freedom in coefficient determination. Coefficient spread can therefore be reduced, resulting in significantly reduced capacitance area in switched-capacitor BPSDM circuits. High-order BPSDMs with different quality factors (Q) are demonstrated. It shows that coefficient spread is significantly reduced, especially for high-Q applications. For comparable eighth-order 3-bit BPSDMs, the maximum coefficient spread are respectively 15369 and 7693 for conventional cascade-of-resonator-with-feedback (CRFB) and cascade-of-resonator-with-feedforward (CRFF) designs, and 114 for the proposed structure. For an eighth-order 1-bit example, these respective values are 8994, 2638, and 74. With coefficient mismatch, peak signal-to-noise ratio (PSNR) degradation of the proposed structure is less than those of the CRFB and CRFF structures, demonstrating reduced sensitivity to component mismatch. Hence, the proposed structure can reduce chip area and ease circuit implementation of BPSDMs.     

On-line adaptive digital correction of dual-quantisation delta-sigma modulators

The authors describe the digital adaptive correction of nonidealities in dual-quantisation delta-sigma modulators. The sources and effects of nonidealities in a delta-sigma loop are discussed, and a simple on-line correction scheme is presented. The theoretical signal-to-noise ratio (SNR) improvement is calculated and simulation results are given which illustrate the effectiveness of the technique.<>     

Granular quantization noise in a class of delta-sigma modulators

The trend toward digital signal processing in communication systems has resulted in a large demand for fast accurate analog-to-digital (A/D) converters, and advances in VLSI technology have made ΔΣ modulator-based A/D converters attractive solutions. However, rigorous theoretical analyses have only been performed for the simplest ΔΣ modulator architectures. Existing analyses of more complicated ΔΣ modulators usually rely on approximations and computer simulations. In the paper, a rigorous analysis of the granular quantization noise in a general class of ΔΣ modulators is developed. Under the assumption that some input-referred circuit noise or dither is present, the second-order asymptotic statistics of the granular quantization noise sequences are determined and ergodic properties are derived     

Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesis

In this paper, rigorous analyses are presented for higher order multistage noise shaping (MASH) Delta-Sigma (/spl Delta//spl Sigma/) modulators, which are built out of cascaded first-order stages, with rational DC inputs and nonzero initial conditions. Asymptotic statistics such as the mean, average power, and autocorrelation of the binary quantizer error are formulated using a nonlinear difference equation approach. An important topic of interest considered here is the fractional-N phase-locked-loop frequency synthesis applications, where the input to the modulator has to be a rational constant. It has been mathematically shown that, regardless of the initial conditions, first-order and second-order MASH /spl Delta//spl Sigma/ modulators with rational DC inputs cannot sufficiently randomize the quantization error samples, and, therefore, are not suitable for fractional-N synthesis applications. An irrational initial condition imposed on the first accumulator of a third or higher order MASH modulator, on the other hand, annihilates the tones throughout the whole output spectrum, and provides a very smooth noise shaping. Simulation results are provided to support the theoretically derived results. Implementation issues of the irrational initial condition in the digital domain are also discussed and investigated together with the effect of finite accumulator size on the noise-shaping quality factor.     

Improved design method for continuous-time quadrature bandpass /spl Sigma//spl Delta/ ADCs

In continuous-time quadrature bandpass /spl Sigma//spl Delta/ ADCs it is desirable to limit the number of cross-couplings. This can be achieved by implementing the loop as a cascade of complex integrators with only real coefficients. It is shown that this may result in a very poor approximation of the desired noise transfer function, because the effect of the DAC pulse is not taken into account correctly. A simple implementation that solves this problem is proposed.     

Systematic design exploration of delta-sigma ADCs

An algorithm for architecture-level exploration of the /spl Delta//spl Sigma/ A/D converter (ADC) design space is presented. Starting from the desired specification, the algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with a single-bit or multibit quantizer, for a range of oversampling ratios. A fast filter-level step evaluates the performance of all loop-filter topologies and passes the accepted solutions to the architecture-level optimization step which maps the filters on feasible architectures and evaluates their performance. The power consumption of each accepted architecture is estimated and the best top-ten solutions in terms of the ratio of peak signal-to-noise+distortion ratio versus power consumption are further optimized for yield. Experimental results for two different design targets are presented. They show that previously published solutions are among the best architectures for a given target but that better solutions can be designed as well.     

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

This paper introduces a possible compensation for finite gain-bandwidth (GBW) induced errors in continuous-time sigma-delta modulators. Therefore, a novel model is derived which reduces the effect of a finite GBW to a corresponding integrator gain-error and feedback loop delays. Thus, previously published methods for the compensation of these errors can be adopted with some modification. The results are confirmed analytically and by simulations and show a possible GBW reduction of about one order of magnitude compared to current designs.     

电流模式带通滤波器设计

随着电子技术的发展,电流模式电路也越来越受到人们的关注,尤其是CCII(第二代电流传输器),本文针对以往电路过于复杂的特点,利用CCII(第二代电流传输器)设计基于单个CCII的带通滤波器电路,该电路仅使用一个CCII和几个R,C元件,与同类电路相比,该电路结构简单,且具有更低的无源灵敏度。     

Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling /spl Delta//spl Sigma/ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the /spl Delta//spl Sigma/ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the /spl Delta//spl Sigma/ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order /spl Delta//spl Sigma/ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25-/spl mu/m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.     

Exact design of switched-capacitor bandpass ladder filters

An exact design of switched-capacitor bandpass filters is presented. This new technique is based on the distributed circuit theory with a suitable bandpass transformation. The theoretical aspects of this method are given as well as the simulated results using a switched-capacitor circuit-analysis program.     

Graphical design of millimeter-wave finline bandpass filters

A very simple yet accurate design procedure for the finline bandpass filters at millimeter wavelengths is presented. The technique enables the geometry of finline bandpass filters to be obtained accurately from simple closed-form equations and curves. Using this graphical approach, various millimeter-wave finline bandpass filters have been designed. Results in V-band (50 to 75 GHz) and W-band (75 to 110 GHz) are presented and indicate a good agreement between the calculated and measured performances.     

A design method of optical bandpass filters

A design method of optical bandpass filters which are composed of several resonators consisting of dielectric layers is discussed. The relation between the loaded Q of a resonator and the thickness of each layer is calculated by treating equivalently each layer as a segment of transmission line and represented on a chart. It becomes possible to design an arbitrary value of loaded Q by using the chart. Thus, an optical bandpass filter of required bandwidth and rejection characteristic can be designed by finding out the optimum thickness of each layer of the resonator which is the component of the filter