Contact resistance for small contacts [MOSFET]

An asymptotic analysis for current flow to small contacts in MOSFET source/drain regions is obtained. The formula for end resistance is compared with numerical simulations. It shows good agreement for contacts whose width is smaller than half the diffusion width     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

A compact scattering model for the nanoscale double-gate MOSFET

An analytically compact model for the nanoscale double gate metal-oxide semiconductor field effect transistor (MOSFET) based on McKelvey's flux theory is developed. The model is continuous above and below threshold and from the linear to saturation regions. Most importantly, it describes nanoscale MOSFETs from the diffusive to ballistic regimes. In addition to its use in exploring the limits and circuit applications of double gate MOSFETs, the model also serves as an example of how semiclassical scattering theory can be used to develop physically sound models for nanoscale transistors     

Accurate modeling of nanoscale gate underlap SOI MOSFET and design of low noise amplifier for RF applications

Paper presents an accurate model by accounting non-quasi-static and extrinsic parasitic effects for 90 nm gate underlap SOI MOSFETs for RF applications. Generated Y-parameters from the model up to 20 GHz matched very well with 2D ATLAS (with an average error of ～5%), whereas results from quasi-static predictive technology model differ significantly (>20%). Calculated transit frequency f _T and maximum frequency of oscillation f _max have been found as ～108 and ～130 GHz respectively. Simulated noise figure at drain-to-source current I _DS ≈ 0.64mA and drain-to-source voltage V _DS=1 V was found to be ≈2.8 dB with gate resistance R _ge = 3 Ω. A low noise amplifier (LNA) designed at operating frequency of 5.8 GHz using the model has shown good match at input (S ₁₁ ≈ ?15 dB), output (S ₂₂ ≈ ?16 dB) and gain (S ₂₁ ≈ 15 dB). A new figure-of-merit of LNA (FoM_LNA) involving signal power gain G, noise factor F and dc power consumption P _dc has been proposed. By comparing with limited available measured data of 180 nm bulk, it has been found that underlap LNA (simulated using the developed model) gives almost three times improvement in the proposed FoM_LNA.     

关于MOSFET的双峰效应量化评估研究

介绍一种关于双峰效应(Double-Hump)的评估方法.通过对MOSFET的Id-Vg曲线的分析,双峰效应的程度可以用数字化评估.采取这种量化表征,细致地研究了双峰效应与掺杂浓度的关系.建立了MOS的Vt 和Punch-through的粒子注入有效浓度和双峰效应的相互关系模型.它们之间的相互关系与现存的理论一致.     

A model too hot to handle? [MOSFET model]

The physics/process-based UFPDB compact model, unified for PDSOI and bulk-Si MOSFETs, has been overviewed. Its truly physical nature was exemplified, and the afforded straightforward evaluation of its single small set of parameters, based on device structure, was discussed. Its predictive capability was demonstrated for devices and circuits, the latter via UFPDB/Spice3 ring-oscillator simulations that benchmarked scaled PDSOI and bulk-Si CMOS technologies, projecting a sustained performance advantage for the former as the devices are scaled to their limit near L_gate=60 nm. Based on the author's development and applications of UFPDB, it is strongly believed that this truly physics-based compact MOSFET model can and should replace the empirical standard, for PDSOI and bulk-Si CMOS at present, and perhaps in the future for fully depleted SOI and double-gate devices     

Two gates are better than one [double-gate MOSFET process]

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.     

Analytical modeling of the partially-depleted SOI MOSFET

An analytical model for the partially-depleted (PD) silicon-on-insulator (SOI) MOSFET above threshold was developed. In contrast to previous models, this model includes front-back interface coupling with all the possibilities associated with it (accumulated, neutral, and depleted back interface). The model applies to tied-body as well as floating-body devices; however, thermal and edge effects are neglected. Interface coupling and floating-body effects are integrated together in a new “unified” algorithm. The “pseudo-two-dimensional” approach (which was used successfully to model lateral fields in bulk-Si devices) is extended to SOI devices. The model is extremely physical and thus highly predictive. Good agreement with experiment was obtained over a wide range of channel lengths and back gate voltages. Because of the model's neglect of thermal effects, however, disagreement was observed at high current levels. A brief physical interpretation of the results is also presented     

Perspectives and challenges in nanoscale device modeling

In this paper, we discuss the role of adequate modelling tools in the development of nanoelectronic technology and devices, including both down-the-roadmap Complementary Metal-Oxide-Semiconductor (CMOS) technology and alternative nanodevices. Such tools can enable understanding of the relevant physical mechanisms on the one hand, and performance evaluation and optimization of device structures, on the other hand. Relevant examples are discussed, drawn by our recent activity, including ballistic strained-silicon Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs), stress-induced leakage currents, nanocrystal memories, and silicon nanowire transistors.     

Noise modeling and measurement techniques [HEMTs]

The high electron mobility transistor's (HEMT's) noise behavior is presented from theoretical and experimental points of view. The general method used in the high-frequency noise analysis is described and the different approximations commonly used in the derivation of the noise parameter expressions are discussed. A comparison between the noise performance of both MESFETs and HEMTs is carried out. The measurement techniques providing the noise figure and the other noise parameters are then described and compared     

The gate bias and geometry dependence of random telegraph signalamplitudes [MOSFET]

A new random telegraph signal (RTS) amplitude model based upon band bending fluctuations has been developed, in contrast to other studies of RTS noise amplitudes, which are derived from RTS fitting parameters, it is demonstrated in this work that noise amplitudes may be predicted from band bending calculations and device DC characteristics. This new model suggests that the decrease in band bending associated with slow-state trapping results in mobility degradation for low gate biases (Coulombic-scattering-limited) and an enhancement in mobility due to vertical field reductions at high gate biases (surface roughness/phonon scattering limited). The band bending formulation shows good correlation with experimental data and accurately predicts the observed dependence upon effective channel length and width     

Anatomy of a spectrum policy court decision [spectrum policy and regulatory issues]

This month?s column reviews a recent U.S. Court of Appeals decision that considered a pectrum policy matter that the Federal Communications Commission (FCC) had decided. This matter should be of interest to readers because it shows how a transparent regulatory system works with a system of checks and balances. Also, many members of this multinational society either work in the United States or develop products for sale in the U.S. market, and thus their work is affected by such decisions.     

Finite-difference time-domain modeling of curved surfaces [EMscattering]

The finite-difference-time-domain (FDTD) method is generalized to include the accurate modeling of curved surfaces. This generalization, the contour path CP), method, accurately models the illumination of bodies with curved surfaces, yet retains the ability to model corners and edges. CP modeling of two-dimensional electromagnetic wave scattering from objects of various shapes and compositions is presented     

A new simplified charge pumping current model and its modelparameter extraction [MOSFET]

Using the Shockley-Read-Hall (SRH) theory, a simple analytic charge pumping current model has been developed and its accuracy verified by exact numerical analysis. It is shown that the derived analytic charge pumping current model with constant capture cross sections for electrons and holes does not correctly simulate the rising (falling) edges of the experimental charge pumping current. According to the slopes of the logarithmic charge pumping current, effective capture-cross-section models for elections and holes are proposed and are incorporated into the developed analytic charge pumping current model. It is shown that the experimental charge pumping current can be simulated very well by using the modified analytic model     

The role of electron trap creation in enhanced hot-carrierdegradation during AC stress [n-channel MOSFET]

Enhanced AC degradation during gate voltage transients is shown to be related to neutral electron traps created at low gate voltages under conditions of hole injection and filled at high gate voltages under conditions of electron injection. During DC stress, where interface state damage dominates, electron trap damage is not seen because the created traps are neutral. In experiments where inductive ringing is eliminated, AC degradation rates are independent of the type of edge (falling versus rising) and independent of the rise/fall time     

Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices

Impact of the intrinsic fluctuations on device characteristics, such as the threshold voltage (V_th) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced V_th fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO₂ for the 1.2 and 0.8 nm EOTs, Al₂O₃ for the 0.4 nm EOT and HfO₂ for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property. Result of this study confirms the suppression of V_th fluctuations with the gate oxide thickness scaling (using high-κ dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device’s scaling and have potential in the nanoelectronics application.