基于PSpice的SiC MOSFET的关键参数建模

分析研究了SiC金属氧化物半导体场效晶体管(MOSFET)各参数与其动、静态特性的内在关系,提出了一种基于PSpice的SiC MOSFET建模新方法。通过引入电压控制电压源对栅极阈值电压进行补偿修正,采用两种不同的结电容模型描述各端电压不同而带来的结电容的变化,并同时增加了MOSFET的漏源电阻、栅极电阻随温度变化的变温度子模型。新模型可全面准确反映SiC MOSFET的动、静态特性,为SiC MOSFET的开关过程分析、损耗计算及主电路设计提供了重要依据。     

高压大功率器件用高温栅偏测试装置研制

为准确评估硅IGBT和碳化硅MOSFET等高压大功率器件不同电应力及热应力条件下的栅极可靠性,研制了实时测量皮安级栅极漏电流的高温栅偏（high temperature gate bias,HTGB）测试装置。此外,该测试装置具备阈值电压在线监测功能,可以更好地监测被测器件的状态以进行可靠性评估和失效分析。为初步验证测试装置的各项功能和可靠性,运用该测试装置对商用IGBT器件在相同温度应力不同电应力条件下进行分组测试。初步测试结果表明老化初期漏电流逐渐降低,最终漏电流大小与电压应力有良好的正相关性,栅偏电压越大,漏电流越大。该测试装置实现了碳化硅MOSFET器件和硅IGBT器件对高温栅偏的测试需求且适用于各种类型的封装。     

SiC MOSFET静态温度特性研究

以实际碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)器件为对象,首先测试了不同温度下的转移和输出特性,获取了温度对其阈值电压、跨导、导通电阻和内栅极电阻的影响规律,接着基于所得到的温度特性实验结果,建立了SiC MOSFET静态等效电路模型,最后对该模型进行了验证。结果表明,温度对SiC MOSFET静态特性及参数的影响较为明显,所建立的等效电路模型能正确反映SiC MOSFET的静态特性。     

考虑变温度影响的SiC MOSFET建模与分析

为了准确反映SiC MOSFET在不同温度下的电气特性,对影响SiC MOSFET电气特性的关键参数进行了分析,提出了一种SiC MOSFET等效电路模型。首先,根据SiC MOSFET阈值电压和跨导随温度变化的规律,采用函数拟合的温控电源模型对SiC MOSFET的阈值电压和漏极电流进行补偿;其次,考虑寄生电容与极间电压的关系,采用电容子电路和可变电容模型对SiC MOSFET的寄生电容进行等效模拟,根据SiC MOSFET体二极管对其静、动态特性的影响,利用独立二极管模型描述体二极管特性,进而建立SiC MOSFET的等效电路模型。最后,在不同温度条件下,对该模型进行了仿真并与实验测试结果进行了对比。结果表明所建模型较为准确地描述SiC MOSFET在较宽温度范围内的静、动态特性,验证了模型的有效性。     

基于开关瞬态反馈的SiC MOSFET有源驱动电路

受内部寄生参数与结电容的影响,碳化硅(SiC)功率器件在高速开关过程中存在极大的电流电压过冲与高频开关振荡,严重影响了SiC基变换器的运行可靠性。因此,该文首先对SiC MOSFET开关特性进行深入分析,揭示栅极电流与电流电压过冲的数学关系;然后提出一种变栅极电流的新型有源驱动电路;通过对SiC MOSFET开关瞬态的漏极电流变化率d I_d/dt、漏-源极电压变换率d V_ds/dt以及栅极电压V_gs的直接检测与反馈,在开关过程的电流和电压上升阶段对栅极电流进行主动调节,抑制电流电压过冲与振荡;最后在多个工况下对本文所提方案进行实验验证。结果表明,与常规驱动方案相比,该文方法减小了30%～50%的电流电压过冲,有效抑制振荡与电磁干扰,提高了SiC MOSFET变换器的运行可靠性。     

碳化硅MOSFET特征参数随温度变化的比较研究

通过对Cree公司三代SiC MOSFET样品在-160~200℃温度下进行测试,提取出每代器件在不同温度下的阈值电压、导通电阻等特征参数。分析比较了三代产品阈值电压、导通电阻随温度的变化趋势,以及不同温度下导通电阻与栅极电压的关系。运用建立物理模型的方法,对三代产品阈值电压、导通电阻各组成部分与温度的关系进行了比较研究。解释了SiC MOSFET的阈值电压的温度变化率随产品更新而逐代降低的原因,是栅极SiO₂/SiC界面存在的陷阱密度在逐代地下降。通过TCAD仿真拟合转移特性随温度的变化,验证了新产品的界面态密度的降低,同时佐证了SiC MOSFET的技术水平在近几年有显著提升。     

1200V/36 A SiC MOSFET短路特性的实验研究

短路能力是衡量功率半导体器件(IGBT、SiC MOSFET等)性能的重要指标,然而SiC MOSFET的短路性能还没有得到充分的研究。为掌握SiC MOSFET在短路工况下的特性,设计一套SiC MOSFET非破坏性短路测试实验平台,从短路脉冲宽度、栅源极电压UGS、栅极电阻RG、漏源极电压UDS、杂散电感LS、壳温度TCASE等方面对1 200 V/36 A SiC MOSFET的短路特性进行全参数实验,综合评估和分析SiC MOSFET器件在不同参数下发生短路的开关瞬态特性。     

半桥结构中的SiC MOSFET串扰电压建模研究

SiC MOSFET凭借着低开关损耗、高工作频率与高工作温度点等优点,逐渐在高效率、高功率密度与高温的应用场合取代传统的硅功率器件。然而,在高速开关中带来的栅极串扰现象严重制约SiC器件的开关速度。传统的串扰抑制方法重点关注由栅极–漏极寄生电容引入的干扰电压,往往通过减小驱动回路阻抗的方式来降低串扰电压。该文基于SiC MOSFET器件的开关模态,提出考虑共源电感的分段线性化串扰电压模型。该模型基于器件数据手册及双脉冲实验提取的参数,考虑栅极–漏极电容、共源电感、体二极管反向恢复等非理想因素的影响。对比不同电压点、电流点与电阻值下实验与模型的输出结果。该模型表明,串扰电压是由器件栅极–漏极电容、共源电感与驱动回路阻抗共同作用的结果。单一降低驱动回路阻抗的方式对串扰电压的抑制效果有限。基于提出的模型,该文给出串扰电压抑制的指导方法,可直接用于SiC MOSFET驱动电路的设计。     

SiC MOSFET串联短路动态特性

在电力电子系统中,因器件击穿、硬件电路缺陷或系统控制失误导致碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)误开通时,桥臂电流回路中多个器件处于开通状态,形成串联短路故障.该文以SiC MOSFET半桥电路为研究对象,详细介绍SiC MOSFET串联短路的动态过程,理论分析负载电流、栅极驱动电压和结温温升对SiC MOSFET短路动态特性的影响规律,推导出SiC MOSFET分压模型,并采用仿真模型进行验证.实验基于1200V/80A SiC MOSFET测试平台验证电路参数对短路损耗和结温分布的影响.理论与实验结果表明,SiC MOSFET串联短路分压特性对电路参数具有较高敏感度,漏极电压与漏极电流不平衡动态变化会改变器件短路损耗,进而影响结温温升,造成串联短路SiC MOSFET不稳定变化.     

考虑器件工作温度影响的Si C功率MOSFET建模

提出一种基于MATLAB/Simulink的SiC功率MOSFET全工作区变温度参数建模方法。在Si基横向双扩散MOSFET模型的基础上,采用与温度相关的电流源和电压源补偿器件漏极电流和阈值电压的变化。通过补充实验拓展SiC功率MOSFET的饱和区工作特性曲线,并根据Si C功率MOSFET的工作特性,采用数学拟合的方法来提取模型参数。在保留各个参数物理意义的同时,摆脱建模过程对物理参数的依赖。在不同电压、电流及温度(25~200℃)的情况下对器件的输出特性、转移特性、阈值电压、导通电阻及开关损耗进行测试,将测试结果与MATLAB/Simulink模型仿真结果进行性比较。模型仿真结果与实际测试结果一致,开关损耗误差在7%之内,验证了模型的准确性及有效性,为实际应用Si C功率MOSFET时系统性能及损耗分析提供参考依据。     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

The Impact of Strain Technology on FUSI Gate SOI CMOSFET

In this paper, the impact of strain engineering on device performance and reliability for fully silicide gate silicon-on-insulator CMOSFET was investigated. With characterizing device's electrical property after hot carrier (HC) and positive/negative bias instability voltage stressing, we found similar enhancement on device performance but different behavior on voltage-stressing-induced device degradation for n/pMOSFETs. Related noise analysis and charge pumping techniques were used to investigate the strain-induced oxide defect which will accelerate device degradation after long-time HC voltage stressing and/or bias instability voltage stressing.      

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Intrinsic reliability projections for a thin JVD silicon nitridegate dielectric in P-MOSFET

A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si₃N₄ gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As a result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si₃N₄ gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability     

单相SVPWM窄脉冲的消除研究

在分析单相电压空间矢量脉宽调制(SVPWM)的原理以及窄脉冲对绝缘栅双极型晶体管(IGBT)的危害的基础上,针对脉宽调制中产生的驱动窄脉冲与关断窄脉冲使IGBT或体二极管在未完全开通时又立刻关断的过程中,器件产生关断电压尖峰和振荡,使得功率开关器件损坏以及在变流中引起的输出波形畸变等问题,通过对调制度M设计的方法,来控制产生的触发驱动脉冲的宽度,达到限制和消除窄脉冲的出现.最后通过Matlab仿真验证了此方法可以使开关器件躲过允许的窄脉冲,增加了电路安全运行的可靠性.     

Effect of the Interfacial $hbox{SiO}_{2}$ Layer in High-$k$ $ hbox{HfO}_{2}$ Gate Stacks on NBTI

A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO₂/SiO₂ gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaV_TH). The metal/high-fc induced traps in the interfacial SiO₂ layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaV_TH and the stress-generated interface trap density DeltaD_IT stress time dependencies. Similar kinetics of the long-term DeltaV_TH(t) and DeltaD_IT(t) dependencies in the high-fe and SiO₂ gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO₂ film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaV_TH and DeltaD_IT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaV_TH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery.     

The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.     

Validity of constant voltage stress based reliability assessment of high-/spl kappa/ devices

Charge trapping in high-/spl kappa/ gate dielectrics affects the result of electrical characterization significantly. DC mobility degradation and device threshold voltage instability and C-V and I-V hysteresis are a few examples. The charging effects in high-/spl kappa/ gate dielectric also affect the validity of conventional reliability test methodologies developed for SiO/sub 2/ devices. In this paper, we review high-/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl kappa/ devices.     

基于大电流通态压降的IGBT功率模块结温监测方法的研究

绝缘栅双极型晶体管IGBT(insulated gate bipolar transistor)是限制新能源汽车可靠性和成本的关键因素。结温监测能够提升IGBT功率模块的功率密度,提高系统可靠性,降低成本。基于此,提出一种基于大电流通态压降的IGBT功率模块结温监测方法。首先分析通态压降与结温之间的关系,然后设计通态压降结温校准电路,并基于小电流通态压降对校准结果进行验证。最后,分别使用数学模型和神经网络模型拟合结温和通态压降的关系,对基于模型对结温进行预测。结果证明,大电流通态压降能够准确测量结温。