Cancellation technique to provide ESD protection for multi-GHz RF inputs

A technique to provide ESD protection for multi-GHz R-F inputs is presented. It provides protection against both human body model (HBM) and charged device model (CDM) type events with minimal effect on RE performance. A 5.25 GHz LNA protected by this means has a measured HBM ESD protection level of 3.6 kV.     

A review on RF ESD protection design

Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits.     

Transmission gate switch for ESD protection of RF pad

A novel transmission gate switch is proposed to effectively replace electrostatic discharge (ESD) protection resistors in CMOS I/O pads. The proposed circuit exhibits a very low on resistance, under normal operation, and a very high off resistance, in the case of ESD stresses. A triple-well CMOS implementation guarantees RF operation and enhanced ESD reliability     

Decreasing-size distributed ESD protection scheme for broad-band RF circuits

The capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broad-band RF circuits due to impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the ESD performance. A new distributed ESD protection structure is proposed to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, called as decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme, which is beneficial to the ESD level. The new proposed DS-DESD protection scheme with a total capacitance of 200 fF from the ESD diodes has been successfully verified in a 0.25-mum CMOS process to sustain a human-body-model ESD level of greater than 8 kV     

A thyristor-only input ESD protection scheme for CMOS RF ICs

We propose an input protection scheme composed of thyristor devices only avoiding usage of a clamp NMOS device to minimize the area consumed by an input pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device in the input pad. The comparison study mainly focuses on robustness against the human body model electrostatic discharge (HBM ESD) in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices, and by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.     

A new ESD protection structure for high-speed GaAs RF ICs

We demonstrate a new electrostatic discharge (ESD) protection structure for high-speed GaAs RF ICs. The structure is composed of small diodes and large transistors using an InGaP heterojunction bipolar transistor (HBT) technology. Its loading effect and its robustness are evaluated experimentally. The impedance of the new structure at OFF state, represented with an equivalent shunt capacitance and an equivalent shunt resistance, are 0.22 pF and 500 /spl Omega/ at 10 GHz. The structure can withstand +2700-V and -2900-V human body model ESD pulses. It can clamp voltage more effectively than the conventional diode-based ESD structure. The new structure can be used to protect 10 Gb/s input/output pins of high-speed RF ICs against ESD.     

Selecting an appropriate ESD protection for discrete RF power LDMOSTs

For ESD protections of RF Power MOSTs, V_t1 lowering by the RF signal - due to the dV/dt effect - can seriously degrade the RF performance. The use of a cascoded protection solves this problem. A new failure mechanism, related to the discharge of on-chip RF matching capacitors is presented. Adding a current limiting resistor in the protection solves this issue. Combining these solutions yields an appropriate protection for discrete RF power LDMOSTs.     

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.     

LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits

The results of a numerical and experimental study aimed at increasing the holding on-state voltage of a low-voltage triggered silicon controlled rectifier are presented. Using TCAD numerical simulations two solutions are presented that are based on emitter injection control by the modification of the emitter–drain area ratio and by the addition of internal diodes in the emitter line. Experimental data generated in a 0.18 μm CMOS technology demonstrate the effectiveness of the new low-voltage triggered silicon controlled rectifier (LVTSCR) structures and validates the simulation results. It has been demonstrated that for the LVTSCR structures with high holding voltage the electrostatic discharge efficiency is 3–5 times higher than that of a conventional grounded gate snapback NMOS and simultaneously has 50% lower RF load capacitance.     

A new low-parasitic polysilicon SCR ESD protection structure for RF ICs

Robust low-parasitic electrostatic discharge (ESD) protection is highly desirable for RF ICs. This letter reports design of a new low-parasitic polysilicon silicon controlled rectifier (SCR) ESD protection structure designed and implemented in a commercial 0.35-/spl mu/m SiGe BiCMOS technology. The concept was verified by simulation and experiment with the results showing that the new structure has much lower parasitic capacitance (C/sub ESD/) and higher F-factor than that of other ESD protection devices. A small polysilicon SCR structure of 750-/spl mu/m/sup 2/ all-inclusive provides a high human body model ESD protection of 3.2 kV while featuring a high F-factor of /spl sim/42 and a low C/sub ESD/ of /spl sim/92.3 fF. The new polysilicon SCR ESD protection structure seems to be an attractive solution to high-GHz RF ICs.     

RF ESD protection strategies: Codesign vs. low-C protection

The present work is focussed on the trade-off between conventional RF ESD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design. A narrow and a broadband RF test circuit were developed to put the benchmark on a firm basis. RF and ESD experiments are discussed, showing where the higher effort for the codesign approach starts to pay off.     

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.     

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.     

Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology

BiCMOS technologies have been used to implement the radio-frequency (RF) integrated circuits (ICs) due to the advantages of low noise, low power consumption, high drive, and high speed. The electrostatic discharge (ESD) is one of the important reliability issues of IC. When the ESD events happen, the ESD protection devices must be turned on immediately to protect the ICs, including the RF ICs in BiCMOS technologies. In this work, the vertical NPN (VNPN) devices in 0.18 μm silicon-germanium (SiGe) BiCMOS technology with base-emitter shorted and resistor trigger approaches are investigated. In component-level, using transmission-line-pulsing (TLP) and ESD simulator test the IV characteristics and human-body-model (HBM) robustness of the VNPN devices, respectively. In system-level, using ESD gun tests the system-level ESD robustness. The ESD protection of VNPN devices are further applied to a 2.4 GHz low-noise amplifier (LNA). After attaching the VNPN devices to LNA, the RF characteristics are not degraded while the ESD robustness can be much improved.     

A plug-and-play wideband RF circuit ESD protection methodology: T-diodes

A novel “plug-and-play” ESD protection methodology for wideband RF applications is demonstrated. This methodology, referred to as T-diodes, utilizes an integrated transformer together with classical ESD protection diodes. The T-diodes act as an artificial transmission line that, when placed as a “plug-and-play” ESD protection component in front of an unprotected wideband LNA, preserves the input matching of that LNA. As a demonstrator, a wideband RF LNA in 0.18 μm CMOS is protected above 4.5 kV HBM ESD robustness without degrading its bandwidth.     

多指条nMOSFET抗ESD设计技术

利用多指条nMOSFET进行抗ESD设计是提高当前CMOS集成电路抗ESD能力的一个重要手段，本文针对国内某集成电路生产线，利用TLP(Transmission Line Pulse)测试系统，测试分析了其nMOSFET单管在ESD作用下的失效机理，计算了单位面积下单管的抗ESD(Electro Static Discharge)能力，得到了为达到一定抗ESD能力而设计的多指条nMOSFET的面积参数，并给出了要达到4000V抗ESD能力时保护管的最小面积，最后通过ESDS试验进行了分析和验证。     

ESD protection methodology for deep-sub-micron CMOS

Electrostatic discharge is considered to be a serious treat of integrated CMOS circuits since the feature size reached about 1.5-1.0μm. Since then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological limitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is concluded that the scaling based limitations might grow to a significant problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular if the high-frequency properties of such technologies should not be affected.     

手机防静电保护—Littelfuse公司的解决方案

手机需要更好的防静电保护 计算机的革命使得电子系统(计算机,外设等设备)之间的通信联接越来越多,因此造成必需要处理的数据量大量膨胀。数据传输的速率也必然随之而提高,并将继续不断地提高。 从历史上来看,电子设备防突变电压的保护随电子技术的进步而改变。固态元件以前,电子真空管是电子设备的主要元件。这些电子真空管器件对静电电压,间接的闪电电压,快速突变的电压(EFT),以及由电子设备本身产生的突变电压     

Pin-pin ESD protection for electro-explosive device under severe human body ESD

Electrostatic discharge (ESD) may introduce huge damages to electro-explosive devices (EEDs). This paper studies the pin-pin ESD protection for EED under server human body ESD. We use the PSpice and MATLAB to simulate the ESD of EED protected with transient voltage suppressor (TVS), varistor, semiconductor arrester and capacitance. Moreover, we achieve the decay time, current waveforms, voltage waveforms and energy integration waveforms of the EED during the ESD, with different protections. Simulation results reveal that TVS succeeded in protecting bridgewire EED against the pin-pin ESD, while other three did not provide adequate protection. The pin-pin ESD experiments have been performed using the TVS and varistor. Experimental results show that, using the TVS protection, the EED is not firing under the severe 50 kV ESD voltage. However, by using varistor protection, the ESD protection capability increases by more than 90%, while the protection capability only enhances by 3.1%. The response time of the TVS, i.e. 10^− 12 s, is much faster than that of the varistor, i.e. 10^− 8 s.     

多电源和多地的片上ESD保护

介绍了集成电路设计中的ESD保护的基本原理和几种常用的保护方法并比较其优劣。提出了在多电源、多地时特殊的ESD保护结构（栅耦合结构及共用泄放回路），以及该结构在不同应用中的变化。