Eigendecomposition of Images Correlated on $S^{1}$, $S^{2}$, and $SO(3)$ Using Spectral Theory

Eigendecomposition represents one computationally efficient approach for dealing with object detection and pose estimation, as well as other vision-based problems, and has been applied to sets of correlated images for this purpose. The major drawback in using eigendecomposition is the off line computational expense incurred by computing the desired subspace. This off line expense increases drastically as the number of correlated images becomes large (which is the case when doing fully general 3-D pose estimation). Previous work has shown that for data correlated on S ¹ , Fourier analysis can help reduce the computational burden of this off line expense. This paper presents a method for extending this technique to data correlated on S ² as well as SO(3) by sampling the sphere appropriately. An algorithm is then developed for reducing the off line computational burden associated with computing the eigenspace by exploiting the spectral information of this spherical data set using spherical harmonics and Wigner-D functions. Experimental results are presented to compare the proposed algorithm to the true eigendecomposition, as well as assess the computational savings.     

Lateral and Vertical Scaling of $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications

In this paper, we have experimentally investigated the impact of lateral and vertical scaling of In_0.7Ga_0.3As high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the In_0.52Al_0.48As insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature V_T = -0.02 V, DIBL = 93 mV/V, S = 88 mV/V, and I_ON/I_OFF = 1.6 times10⁴, at V _DD = 0.5 V. We also estimate a gate delay of CV/I = 1.6 ps at V_DD = 0.5 V. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit 1.2times more current drive (I_ON) than the state-of-the-art 65-nm low-power CMOS technology at V _DD = 0.5 V.     

Influence of Ho-Doping on the Electromagnetic Field-Dependent $E$–$J$ Characteristics of (Bi,Pb)-2212 Superconductor

The magnetic field (B ) dependence of electric field versus transport current density (E-J characteristics) of Bi_1.6Pb_0.5Sr_2-xHo_xCa_1.1Cu_2.1O_8+delta superconductor was studied for x from 0.000 to 0.200. The behavior of supercurrent flow under magnetic fields in Ho-doped (Bi,Pb)-2212 is explained using thermally activated flux-creep. The n -value and characteristic pinning energy ( U_c) estimated from E-J characteristics show that at applied fields, the flux-lines in Ho-doped samples are in the glass-state. A correlation is observed between n -index and J_c of doped samples. The highly enhanced critical current density (J_c) and n-index in both self- and applied-fields due to Ho-doping is of great scientific and technological significance.     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

A Time-Variant Analysis of Fundamental $1/f^{3}$ Phase Noise in CMOS Parallel $LC$ -Tank Quadrature Oscillators

This paper presents a rigorous time-variant analysis of the 1/f MOS device noise upconversion into 1/f phase noise for two of the most popular parallel-coupled quadrature CMOS harmonic oscillators. Simple closed-form equations for the fundamental 1/f ³ phase-noise spectrum are derived and validated through SpectreRF simulations, proving that the two topologies display remarkably different sensitivities to the low-frequency noise sources. Based on the developed analysis, useful general design insights are also presented.     

A $Q$– $f$ Droop Curve for Facilitating Islanding Detection of Inverter-Based Distributed Generation

This paper presents a new method for islanding detection of distributed generation (DG) inverter that relies on analyzing the reactive power versus frequency (Q-f) characteristic of the DG and the islanded load. The proposed method is based on equipping the DG interface with a Q-f droop curve that forces the DG to lose its stable operation once an islanding condition occurs. A simple passive islanding detection scheme that relies on frequency relays can then be used to detect the moment of islanding. The performance of the proposed method is evaluated under the IEEE 1547 and UL 1741 antiislanding test configuration. The studies reported in this paper are based on time-domain simulations in the power systems computer-aided design (PSCAD)/EMTDC environment. The results show that the proposed technique has negligible nondetection zone and is capable of accurately detecting islanding within the standard permissible detection times. In addition, the technique proves to be robust under multiple-DG operation.     

22.7-dB Gain $-$19.7-dBm $ICP_{1{rm dB}}$ UWB CMOS LNA

A fully differential CMOS ultrawideband low-noise amplifier (LNA) is presented. The LNA has been realized in a standard 90-nm CMOS technology and consists of a common-gate stage and two subsequent common-source stages. The common-gate input stage realizes a wideband input impedance matching to the source impedance of the receiver (i.e., the antenna), whereas the two subsequent common-source stages provide a wideband gain by exploiting RLC tanks. The measurements have exhibited a transducer gain of 22.7 dB at 5.2 GHz, a 4.9-GHz-wide B _3dB, an input reflection coefficient lower than -10.5 dB, and an input-referred 1-dB compression point of -19.7 dBm, which are in excellent agreement with the postlayout simulation results, confirming the approach validity and the design robustness.     

Restricted Isometry Constants Where $ell ^{p}$ Sparse Recovery Can Fail for $0≪ p leq 1$

This paper investigates conditions under which the solution of an underdetermined linear system with minimal lscr^p norm, 0 < p les 1, is guaranteed to be also the sparsest one. Matrices are constructed with restricted isometry constants (RIC) delta_2m arbitrarily close to 1/radic2 ap 0.707 where sparse recovery with p = 1 fails for at least one m-sparse vector, as well as matrices with delta_2m arbitrarily close to one where lscr¹ minimization succeeds for any m-sparse vector. This highlights the pessimism of sparse recovery prediction based on the RIC, and indicates that there is limited room for improving over the best known positive results of Foucart and Lai, which guarantee that lscr¹ minimization recovers all m-sparse vectors for any matrix with delta_2m < 2(3 - radic2)/7 ap 0.4531. These constructions are a by-product of tight conditions for lscr^p recovery (0 les p les 1) with matrices of unit spectral norm, which are expressed in terms of the minimal singular values of 2m-column submatrices. Compared to lscr¹ minimization, lscr^p minimization recovery failure is shown to be only slightly delayed in terms of the RIC values. Furthermore in this case the minimization is nonconvex and it is important to consider the specific minimization algorithm being used. It is shown that when lscr^p optimization is attempted using an iterative reweighted lscr¹ scheme, failure can still occur for delta_2m arbitrarily close to 1/radic2.     

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- V t and dual- T _ox assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.     

Development of an Ultrafast On-the-Fly $I_{rm DLIN}$ Technique to Study NBTI in Plasma and Thermal Oxynitride p-MOSFETs

An ultrafast on-the-fly technique is developed to study linear drain current (I _DLIN) degradation in plasma and thermal oxynitride p-MOSFETs during negative-bias temperature instability (NBTI) stress. The technique enhances the measurement resolution (ldquotime-zerordquo delay) down to 1 mus and helps to identify several key differences in NBTI behavior between plasma and thermal films. The impact of the time-zero delay on time, temperature, and bias dependence of NBTI is studied, and its influence on extrapolated safe-operating overdrive condition is analyzed. It is shown that plasma-nitrided films, in spite of having higher N density, are less susceptible to NBTI than their thermal counterparts.     

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si_0.77Ge_0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm^-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.     

2$,times,$ 2 InP Optical Switching Matrix Based on Carrier-Induced Effects for 1.55-$mu$m Applications

This letter demonstrates a 2times2 low optical crosstalk and low power consumption switching matrix device based on carrier-induced effects on an InP substrate. The matrix device comprises two digital optical switches (DOSs) with a wide multimode Y-junction associated with a sinusoidal passive integrated optical circuit with an optimized X-crossing. The passive structure was designed using a two-dimensional beam propagation method (BPM) and the entire InP-InGaAsP-InP DOS was designed using a semivectorial three-dimensional BPM. The fabricated 2times2 InP switching matrix heterostructure with lambdag=1.3 mum exhibits optical crosstalk as low as -30.5 dB for drive current of 52 mA at 1.55-mum wavelength. Maximum crosstalk change of 4 dB is measured under optical polarization variation.     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Analytical Model of $I$– $V$ Characteristics of Arbitrarily Shallow p-n Junctions

For the first time, an analytical model of arbitrarily shallow p-n junctions is presented. Depending on the junction depth, electrical characteristics of ultrashallow p-n junctions can vary from the characteristics of standard Schottky diodes to standard deep p-n junctions. This model successfully unifies the standard Schottky and p-n diode expressions. In the crossover region, where the shallow doping region can be totally depleted, electrical characteristics phenomenologically substantially different from typical diode characteristics are predicted. These predictions and the accuracy of the presented model are evaluated by comparison with the MEDICI simulations. Furthermore, ultrashallow $hbox{n}^{+}$-p diodes were fabricated, and the anomalous behavior in the crossover regime was experimentally observed.      

Performance of $n$-Type InSb and InAs Nanowire Field-Effect Transistors

The electronic structure of highly scaled InSb and InAs nanowire (NW) field-effect transistors (FETs) is calculated with an eight-band ${bf k} cdot {bf p}$ model. Cross sections of 4 nm or less result in bandgaps of 0.8 eV or more. For these cross sections, all devices are single moded and operate in the quantum capacitance limit. Analytical expressions for the transconductance, cutoff frequency, and gate delay time are presented and compared to numerical results. The dependence of the intrinsic cutoff frequency on drive current is weak, scaling as $sqrt{I_{D}}$ with values in the 4–7 THz range that are good for RF applications. The gate delay times strongly depend on the drive current, scaling as $I_{D}^{-3/2}$ with values ranging from 25 to 132 fs which are competitive for digital applications.      

Metal–Oxide–High-$kappa$ Dielectric–Oxide–Semiconductor (MOHOS) Capacitors and Field-Effect Transistors for Memory Applications

Metal-oxide-high-kappa dielectric-oxide-silicon capacitors and transistors are fabricated using HfO₂ and Dy₂O₃ high-kappa dielectrics as the charge storage layer. The programming speed of Al/SiO₂/Dy₂O₃/ SiO₂/Si transistor is characterized by a DeltaV _th shift of 1.0 V with a programming voltage of 12 V applied for 10 ms. As for retention properties, the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors can keep a DeltaV _th window of 0.5 V for 2 times10⁸ s. The corresponding numbers for Al/ SiO₂/HfO₂/SiO₂/Si transistors are 100 ms and 2 times10⁴ s, respectively. The better performance of the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface.     

The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.