基于遗传算法的低功耗有限状态机状态分配

提出一种通过状态分配来实现有限状态机的功耗和面积同时优化的方法．在分析现有成本函数的基础上，提出了一个新的成本函数，并利用遗传算法能进行多目标优化的能力来实现功耗和面积的同时优化．该算法用C语言实现，并对17个MCNC有限状态机标准电路进行测试．测试结果表明，与已有的功耗优化算法相比，文中算法在功耗和面积方面有一定的优势．     

面向多级逻辑的低功耗有限状态机状态分配

状态分配在低功耗有限状态机设计中已经被证明是很有效的方法.该文针对有限状态机多级组合逻辑实现提出了一个新的成本函数,并利用整体退火遗传算法来进行状态码的搜索,通过减少电路的开关活动性和组合逻辑部分的面积来达到功耗的降低.对25个有限状态机标准测试电路进行面积和功耗的测试表明:与已发表的针对面积和功耗优化的算法相比,该文所提出的算法不但在功耗降低上具有较大的改进,在面积改善上也具有一定的优势.     

改进模拟退火遗传算法的3D NoC低功耗映射

功耗优化是NoC设计的重要部分,针对将IP (intellectual property)核合理映射NoC的问题,提出一种初始种群优化的模拟退火遗传映射算法.首先以功耗优化为主要目标,通过对初始种群选取方法进行改进来获取功耗更低的映射方案,并针对遗传算法局部最优问题,在遗传算法交叉操作阶段结合模拟退火算法,得到全局最优方案.实验在Windows系统下采用C++语言实现,结果显示,与传统的遗传算法相比,该算法具有较好的收敛性,能快速搜索到较优解,在124个IP核的情况下,采用改进的模拟退火遗传算法进行映射产生的平均功耗比使用遗传算法时降低了32.0%.     

考虑热效应的资源数量分配算法

芯片上局部的高温对集成电路有很多负面影响.目前已有的行为级综合算法只是在资源绑定阶段降低峰值温度,忽视了资源数量分配阶段对峰值温度的影响.为此,提出一种资源数量分配算法,根据前一个综合结果的功耗密度以及经热分析得到的温度反馈调整各种资源的使用量,使不同种类资源间的功耗密度接近平均分布,从而达到降低峰值温度的效果.实验结果表明,该算法在增加2.0%面积的情况下能平均降低峰值温度9.4℃.     

低剩磁误差磁通门的激励电路研究

降低磁通门剩磁误差的有效方法是增大激励电流的峰值,但大的激励电流峰值将增大功耗.带有足够高峰值的尖脉冲激励电流能降低剩磁误差,同时也降低了功耗,但是降低了传感器的灵敏度而且信号的处理难度增加.一种有效的解决方法是采用激励调谐方法获得所谓理想激励波形.本文提出用激励电路产生高峰值和低有效值激励信号的方法.与调谐激励方法不同,该方法采用积分器和微分器对输入方波信号进行处理后相加,得到一种在峰值处叠加有尖脉冲的三角波信号.电路不用仔细调谐,且尖脉冲的峰值比较容易调节,方便对剩磁误差的研究.针对尖脉冲的峰值固定的情况,还提出了仅由两个电阻,两个电容和一个运算放大器组成的改进型电路.实验结果表明:采用本文激励电路,在10 mT的磁场干扰后,磁通门的剩磁误差为0.5nT.     

一种考虑电压岛边界约束的多电压布图算法

多电压设计(multiple supply voltage,MSV)是降低SoC功耗的有效方法之一.为便于电压岛供电引脚的放置,提出了一种考虑电压岛边界约束的多电压布图算法.首先,基于切分树表示的布图解特点,提出一种边界检查算法快速确定所有模块的边界信息.其次,以优化功耗为目标采用改进动态规划方法进行多电压分配并构建电压岛.最后,以模拟退火算法作为搜索引擎对芯片的面积、线长和功耗进行协同优化.为减少SA迭代次数,采用了一个两阶段的降温策略.对GSRC电路的实验结果表明,该算法可获得满足边界约束的多电压布图,且和不考虑边界约束时相比,仅在功耗上平均增加5.2％.     

基于连续探索型遗传算法的多峰值函数的优化

提出了一种连续探索型遗传算法．它不仅能提高简单遗传算法的收敛速度．而且能有效地保证种群的多样性，在全局范围内搜索解空间．得到最优解．将算法应用于多峰值函数的优化．仿真表明该算法的有效性和效率性．     

电池特性驱动的变电压任务调度

研究了变电压任务调度技术在电池能效优化领域中的应用,通过全面分析与电池能效相关的非线性特性,提出启发式的电池非线性特性驱动的变电压任务调度算法．该算法能有效地利用系统空闲时间优化电池放电电流分布,从而提高电池能效,降低目标任务执行消耗的能量．实验结果表明,该算法能够将执行目标任务消耗的能量降低30％以上,同时降低系统峰值功耗和平均功耗．     

CMOS电路晶体管级功耗优化方法

随着集成电路工艺进入纳米时代,在集成电路设计约束重要性方面,功耗已成为与性能等量齐观的设计约束.由于缺少有效的晶体管级时延模拟器,所以现有的低功耗设计技术均为逻辑门级功耗优化方法.受惠于更低的优化颗粒度,晶体管级优化方法具有比逻辑门级方法更强的静态功耗优化能力,因此针对高静态功耗的纳米工艺芯片,开展晶体管级优化方法的研究具有非常重要的意义.基于晶体管级VLSI模拟器,提出了一种新的晶体管级优化方法用于进一步降低静态功耗,它由两个算法步骤构成:先用聚团策略(clustering)在逻辑门空间来提高优化算法的效率,再用粒度较小的晶体管空间优化算法来提高功耗的优化效果.实验证明所提方法具有以下优点:1) 该方法适用范围较广,可以分析和优化各种电路.这些电路中,每个晶体管都可以有不同的阈值电压V T0、沟道宽度W和沟道长度L.2) 该方法的功耗优化效果较好.在晶体管级W VT0 L的功耗优化实验中,该方法在不降低动态功耗优化效果的前提(动态功耗平均仅增加0.02%)下,在合理的运行时间(优化C7552仅用856.4s)内,在晶体管级对逻辑门级优化结果进行进一步优化,使静态功耗得到进一步降低,平均降低22.85%,最大降低43%.     

基于二进制粒子群与遗传算法的数据分配研究

针对目前分布式数据库数据分配方法法存在寻求最优分配方案和运行效率等问题的不足,在基于改进的遗传算法的数据分配方法基础上,引入二进制粒子群算法,提出了一种基于二进制粒子群与遗传算法的数据分配方法,既具有二进制粒子群算法的运行速度快、记忆功能好等特点,又具有遗传算法的全局搜索能力、变异能力等特点。该分配方法能够提高搜索效率,并且快速有效地获得全局最优解。实验结果表明,所提出的数据分配方法在搜索全局最优解方面优于基于遗传算法的分配方法,在搜索速度方面比枚举法的分配方法和基于遗传算法的分配方法更快。     

Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization

Finite state machine （FSM） plays a vital current which is drawn by state transitions can result in role in the sequential logic design. In an FSM, the high peak large voltage drop and electromigration which significantly affect circuit reliability. Several published papers show that the peak current can be reduced by post-optimization schemes or Boolean satisfiability （SAT）-based formulations. However, those methods of reducing the peak current either increase the overall power dissipation or are not efficient. This paper has proposed a low power state assignment algorithm with upper bound peak current constraints. First the peak current constraints are weighted into the objective function by Lagrangian relaxation technique with Lagrangian multipliers to penalize the violation. Second, Lagrangian sub-problems are solved by a genetic algorithm with Lagrangian multipliers updated by the subgradient optimization method. Finally, a heuristic algorithm determines the upper bound of the peak current, and achieves optimization between peak current and switching power. Experimental results of International Workshop on Logic and Synthesis （IWLS） 1993 benchmark suites show that the proposed method can achieve up to 45.27% reduction of peak current, 6.31% reduction of switching power, and significant reduction of run time compared with previously published results.     

Sequential algorithm for low-power encoding internal states of finite state machines

A heuristic method for encoding internal states (state assignment) of finite state machines (FSMs) so as to reduce their power consumption is proposed. A feature of the proposed approach is that the state assignment procedure takes into account the activity function of the memory elements when the FSM transits from a current state to other states that have already been encoded. A procedure for determining the power consumption of the FSM based on the codes of its internal states and probabilities of appearance of units at each input of the FSM is described. Experiments showed that the proposed approach makes it possible to reduce the power consumption of the FSM by 39% on the average compared with the NOVA algorithm and sometimes by 68%. In conclusion, the possibilities of improving the performance of the proposed algorithm in the synthesis of a specific FSM are discussed and promising directions of further research are indicated.     

Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits

In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.     

时延约束下快速门级双电压分配算法

针对门级电压分配算法速度慢的问题,提出了一种时延约束下基于门分组的双电压分配算法。通过门工作在低、高电压下的延时差与时延裕量的比较,将门分为高电压门组和低电压门组;针对违反时延约束的关键路径上的低电压门（称为关键低电压门）,采用最小割法逐渐升高其电压至电路满足时延约束。通过对ISCAS’85标准电路测试的实验结果表明,与已发表的算法比较,不但功耗有一定改进,且算法速度快。     

Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits

State assignment (SA) for finite state machines (FSMs) is one of the main optimization problems in the synthesis of sequential circuits. It determines the complexity of its combinational circuit and thus area, delay, testability and power dissipation of its implementation. Particle swarm optimization (PSO) is a non-deterministic heuristic that optimizes a problem by iteratively trying to improve a candidate solution with regard to a given measure of quality. PSO optimizes a problem by having a population of candidate solutions called particles, and moving them around in the search-space according to a simple mathematical formulae. In this paper, we propose an improved binary particle swarm optimization (BPSO) algorithm and demonstrate its effectiveness in solving the state assignment problem in sequential circuit synthesis targeting area optimization. It will be an evident that the proposed BPSO algorithm overcomes the drawbacks of the original BPSO algorithm. Experimental results demonstrate the effectiveness of the proposed BPSO algorithm in comparison to other BPSO variants reported in the literature and in comparison to Genetic Algorithm (GA), Simulated Evolution (SimE) and deterministic algorithms like Jedi and Nova.     

Reset: A Reconfigurable state encoding technique for FSM to achieve security and hardware optimality

Digital controllers are prone to side-channel and fault-insertion attacks that lead hardware security as the primary issue in its creation. On the other hand, optimal hardware design is also the prime concern while crafting a digital controller. A finite state machine (FSM) presents a novel framework for any complex digital controller, and a state assignment technique is used for its optimization. In this article, a reconfigurable state encoding technique (ReSET) is proposed for FSM to obtain security and hardware optimality. ReSET is a deterministic method, which employs algorithms such as, (a) robust quadratic sum code based state assignment, and (b) gradient-based interior point approach based state assignment. A user-defined reconfiguration factor is introduced in ReSET by which the degree of security and hardware optimality is configured for the FSM. An extensive set of experiments are executed to validate the ReSET’s feasibility, which also proves ReSET’s superiority in terms of area, computation time, power, and error masking probabilities over the state-of-art literature. To the best of author’s knowledge, ReSET has made the first successful attempt to achieve security as well as hardware optimality for an FSM by setting the reconfiguration factor.     

Inducing finite state machines from training samples using ant colony optimization

A method for control finite state machine (FSM) induction in which an ant colony optimization algorithm is used for search optimization is proposed. The efficiency of this method is estimated using the generation of FSMs for controlling a model of an unmanned aerial vehicle (UAV). It is shown that the proposed method outperforms the method based on genetic algorithms both in terms of performance and quality.     

划分有限状态机的低功耗实现模型

通过引入映射状态,使得单状态机的状态分配算法可直接应用于被划分的有限状态机,提出了实现划分有限状态机的通用物理模型.对13个MCNC基准电路,采用文中模型进行测试,实验结果与已发表的结果相比,文中模型在功耗和面积的改进方面有一定的优势.