可重构Viterbi基核单元的设计与实现

为适应多种通信标准,提出了一种新的可重构Viterbi译码器基核单元,由该基核单元可动态重构成不同约束长度(3~9)、不同编码效率(1/2或1/3)以及不同生成多项式的Viterbi译码器。在Xilinx Virtex4系列FPGA上,对该基核单元组成的译码器进行综合实现,并进行了仿真。结果表明,该译码器的速度能达到50 Mbps,适合在802.11无线局域网及3G网络中使用。     

基于IEEE 802.11a标准的解码器设计

基于IEEE 802.11a标准,设计并实现了一个新的解码器方案。方案中采用了软判决解映射;提出了一种并行添零方法;设计了一种全并行的Viterbi译码器,采用矢量差的"1范数"代替欧氏距离作为软判决译码距离。可以保证译码器性能、明显提高译码速度,并有效降低硬件实现的复杂度。通过计算机仿真和硬件调试,验证了该解码器的良好性能。     

Viterbi译码器的应用及其硬件设计与实现

维特比译码器是人们广泛采用的卷积码的译码器,在IS-95,GSM,3GPP中都有广泛的应用.文中首先简单说明Viterbi译码算法原理,接着分析Viterbi译码算法设计及伪代码实现,根据TD-SCDMA卷积码编码方案,设计了一种采用软判决方式的维特比译码器,并采用合理的归一化方式,保证了计算路径值的过程中不会发生溢出.仿真表明:改进的译码器具有良好的性能.     

TD—SCDMA系统中Viterbi算法研究与改进

文中首先简单地说明Viterbi译码算法原理，接着分析Viterbi译码算法设计及伪代码实现，然后根据软判决和硬判决对译码性能的影响以及改进的译码器和MATLAB库函数的译码器作了仿真比较．仿真表明：改进的译码器具有良好的性能．     

一种基于FPGA的Viterbi译码器

介绍了一种(2，1，6)删余生成的(3，2，6)卷积码的Viterbi译码器的FPGA实现方法。该译码器基于软判决设计，约束长度为7。在具体实现中采用了全并行的处理方法，提高了译码速率。     

2,1,7卷积码Viterbi译码器的一种设计方案

卷积码在通信系统中得到了极为广泛的应用.其中约束长度K=7,码率为1/2和1/3的Odenwalder卷积码已经成为商业卫星通信系统中的标准编码方法.提出了一种(2,1,7)卷积码Viterbi译码器的设计方案,该译码器采用全并行结构的加/比/选模块和回溯法以提高译码速度,重点介绍了幸存路径存储与交换单元的设计与实现.     

一种基于FPGA的Viterbi译码器的研究与设计

针对通信系统中传统维特比(Viterbi)译码器结构复杂、译码延时大、资源消耗大的问题,提出了一种新的基于FPGA的Viterbi译码器设计。结合(2,1,7)卷积编码器和Viterbi译码器的工作原理,设计出译码器的核心组成模块,具体采用3比特软判决译码,用曼哈顿距离计算分支度量,32个碟型加比选子单元并行运算,完成幸存路径和幸存信息的计算。幸存路径管理模块采用Viterbi截短译码算法,回溯操作分成写数据、回溯读和译码读,以改进的流水线进行并行译码操作,译码延时和储存空间分别降低至和。     

Viterbi译码器的硬件实现

介绍了一种Vkerbi译码器的硬件实现方法。设计的基于硬判决的Viterbi译码器具有约束长度长（9)、译码深度深（64)的特点。为了兼顾硬件资源与电路性能两个方面，在设计中使用了4个ACS单元，并根据Xilinx Virtex系列FPGA的结构特点．利用FPGA内部的BlockRAM保存汉明距离和幸存路径，提高了译码速度。     

基于FPGA的卷积码Viterbi译码器性能研究

基于FPGA的卷积码Viterbi译码器,其性能与译码算法参数设置密切相关。在采用VHDL语言设计实现译码器的基础上,通过仿真,分析了Viterbi译码器参数的设置情况,就幸存路径长度、编码存储度等参数对FPGA译码器性能的影响进行了讨论,并给出了这些参数的最佳取值。对卷积码编译码参数设计具有较好的指导性和实用性。     

海事卫星标准C通信船站Viterbi译码器设计

本文针对海事卫星标准C通信船站的特点,介绍用高速DSP TMS32020芯片设计Viterbi译码器的过程。实验结果证明,在解调器输出八电平软判决时,译码器在P_b=10~(-5)处可获得5dB的编码增益,而且体积小、重量轻,基本达到了标准C通信船站的实用要求。     

A modular bit-serial architecture for large-constraint-lengthViterbi decoding

A node-parallel Viterbi decoding architecture and bit-serial processing and communication are presented. An important aspect of this structure is that short-constraint-length decoders may be interconnected, without loss of throughput, to implement a Viterbi decoder of larger constraint length. The convolutional encoder trellis is modeled by appropriate wiring of decoder processing nodes: a variety of generating codes can be accommodated. Bit-serial communication links between nodes require only a single wire each and thus interconnection area is relatively small. During each decoding cycle, more than 50 b need to be communicated on each serial link and thus the technique is limited to moderate bit rate applications. A constraint length K=4 `proof of concept' chip was developed using 9860 transistors in 3 μm CMOS on a 4.51-mm×4.51-mm die size. The complete circuit operates at 280 kb/s and supports any rate 1/2 or 1/3 code with eight-level soft decision     

Single carrier digital terrestrial television broadcasting

A transmission system for digital terrestrial television broadcasting has been designed. This system is based on the European cable system but uses stronger error correction and better equalization. The stronger error correction is a concatenation of Reed Solomon coding RS [204,188,17] and convolutional coding with R_conv=1/2, 2/3, 3/4, 5/6 and 7/8. The algorithm which is used for convolutional decoding is the Viterbi algorithm. To provide the Viterbi decoder with soft decision information, every symbol bit will be expanded with two soft decision (reliability) bits. The modulation scheme of the terrestrial transmission system is 64-QAM square root raised cosine filtered with a roll off factor α=0.15. The mapping of the symbols into the 64-QAM constellation is a Gray-mapping over the complete I,Q-plane. In this paper the performances of the terrestrial transmission system are simulated and analyzed     

Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network

Two reinforcement learning neural network architectures which enhance the performance of a soft-decision Viterbi decoder used for forward error-correction in a digital communication system have been investigated and compared. Each reinforcement learning neural network is designed to work as a co-processor to a demodulator dynamically adapting the soft quantization thresholds toward optimal settings in varying noise environments. The soft quantization thresholds of the demodulator are dynamically adjusted according to the previous performance of the Viterbi decoder, with updates occurring in fixed intervals (every 200 decoded bits out of the Viterbi decoder.) To facilitate implementaiton in digital hardware, each weight of the neural network and related parameters are specified as binary numbers. Computer simulation results demonstrate that, on average, the performance of a Viterbi decoder on an AWGN channel with nonuniformly-spaced soft decision thresholds dynamically adjusted by these neural networks is better than the performance of a Viterbi decoder with uniformly-spaced thresholds. This approach may be used for a variety of other digital communication applications such as channel estimation, adaptive equalization, and signal acquisition.     

Performance analysis of Viterbi decoder using channel stateinformation in COFDM system

This paper relates to the application method of channel state information (CSI) to the Viterbi (maximum likelihood) decoder in the digital terrestrial television broadcasting system. The proposed Viterbi decoder uses the CSI derived from the pilots inserted in the transmitter of the COFDM (coded orthogonal frequency division multiplexing) system. The CSI is calculated by interpolation using the pilots in the receiver. The active real (I) and imaginary (Q) data after equalization are transferred to the branch metric calculation block that decides the euclidean distance for soft decision decoding and also the estimated CSI values are transferred to the same block. After calculating the euclidean distance for the soft decision decoding, the euclidean distance of the branch metric is multiplied by CSI. To do so, new branch metric values that consider each carrier state information are obtained. We simulated this method in Rayleigh fading defined in the ETSI standard. From the simulation, this method has better performance of about 0.15 dB to 0.7 dB and 2.2 dB to 2.9 dB in the Rayleigh channel than that of conventional soft decision Viterbi decoding with or without a bit interleaver where the constellation is QPSK, l6-QAM and 64-QAM     

DSD (double soft decision) concatenated FEC scheme in mobilesatellite communication systems

In order to realize a higher-code-gain forward error correction scheme in mobile satellite communication systems, a novel concatenated coding scheme employing soft decision decoding for not only inner codes but also outer codes (double soft decision, or DSD, concatenated forward error correction scheme) is proposed. Soft-decision outer decoding can improve the bit error probability of inner decoded data. In this scheme, likelihood information from an inner Viterbi decoder is used in the decoding of outer codes. A technique using the path memory circuit status 1.0 ratio for likelihood information is proposed, and is shown to be the most reliable even though it requires the simplest hardware among the alternative methods. A computer simulation clarifies that the DSD scheme improves Pe performance to one-third of that of the conventional hard-decision outer decoding. Moreover, to reduce the interleaving delay time in fading channels or inner decoded data of concatenated codes, a parallel forward error correction scheme is proposed     

维特比译码的仿真与实现

维特比译码算法是一种最大似然序列检测的方法,首先分析仿真了在不同判决方式和回溯深度下的维特比译码的性能,得出结论:在无线高斯信道中,维特比译码采用3比特软判决及回溯深度为48的时候,系统能达到最佳的效果;利用上述结论使用Q1900芯片实现了维特比译码。     

卷积编码及译码在数字通信系统中的仿真

本文介绍了利用点对点（哪）数字通信系统模型，推导卷积编码和Viterbi译码的非线性传输函数的方法以及对Viterbi译码软判决和硬判决的性能分析。通过Matlab中的Simulink仿真模块，对系统模型进行了建模，其仿真结果表明。增大卷积编码和Viterbi译码的约束长度可以提高误码性能。最后，得到了Viterbi译码在软判决和硬判决条件下的误码曲线。     

Performance Bounds for Convolutional Codes with Digital Viterbi Decoders in Gaussian Noise

With digital implementations of the Viterbi decoding algorithm for convolutional codes, soft quantization is preferred over hard quantization because it generally yields superior performance. Since the decoder needs to know the signal energy and channel noise variance with soft quantization, inaccurate information can result in a mismatch between the channel and decoder. Bounds which are tight for high signal-to-noise ratios are obtained on the bit error probability using the generating function approach. Automatic gain control level inaccuracies, imperfect carrier phase, symbol timing synchronization error, and path metric digitization are discussed in the context of a mismatch between the channel and decoder.     

Performance of multi-bit differential SQAM in mobile radio channel

A new multi-bit DSQAM (differential superposed quadrature amplitude modulation) for use in bandwidth and power limited digital mobile radio is proposed. A DSQAM signal is generated by a differentially encoded SQAM processor, and is detected by a multi-bit differential receiver combined with a soft decision Viterbi decoder. The simulated BER result shows that, in an AWGN channel, a 5 bit DSQAM modem achieves a 7.2 dB E_b/N₀ improvement over a conventional 1 bit differential receiver. In Rician fading channels, DSQAM demonstrates a high degree of robustness suffering only a minor loss of signal     

大约束度Viterbi译码器中路径存储单元的设计

维特比(Viterbi)译码器由于其优良的纠错性能,在通信领域有着十分广泛的应用。用FPGA实现Viterbi译码算法时,其硬件资源的消耗与译码速度始终是相互制约的两个方面,通过合理安排加比选单元和路径度量存储单元可有效缓解这一矛盾。基于基4算法所提出的同址路径度量存储管理方法能在提高译码速度同时有效降低译码器的硬件资源需求。