倒装芯片底部填充工艺

从热疲劳故障的角度论述了倒装芯片底部填充的必要性，介绍了倒装芯片底部填充的参数控制。通过正确的底部填充，可提高倒装芯片组装的成品率和可靠性。     

倒装芯片的可修复底部填充技术

板上芯片技术(Chip-on-Board简称COB),也称之为芯片直接贴装技术(Direct Chip Attach简称DCA),是采用粘接剂或自动带焊、丝焊、倒装焊等方法,将裸露的集成电路芯片直接贴装在电路板上的一项技术。倒装芯片是COB中的一种(其余二种为引线键合和载带自动键合),它将芯片有源区面     

倒装芯片的底部填充材料和涂布

倒装芯片是当今半导体封装领域的一大热点,它既是一种芯片互连技术,更是一种理想的芯片粘接技术。以往后级封装技术都是将芯片的有源区面朝上,背对基板粘贴后键合(如引线键合和载带自动键合TAB)。而倒装芯片则是将芯片有源区面对基板,通过芯片上呈阵列排列的焊料凸点来实现芯片与衬底的互连。显然,这种芯片互连的方式能够提供更高的I/O密度。     

关于底部填充在倒装芯片应用中空洞缺陷的影响因素

底部填充包封材料起初应用于提高早期氧化铝（Al2O3）基材的倒装芯片的可靠性。在芯片最外围的焊点易疲劳而导致芯片功能失效．相对较小的硅片和基材间的热膨胀差异是芯片在经受热循环时产生这种问题的根源．这样，热循环的温度范围及循环的次数就决定了芯片的使用寿命．在芯片和基板间填充可固化的包封材料，可以很好地把热膨胀差异带来的集中于焊点周围的应力分散到整个芯片所覆盖的范围。 随着引入环氧材料作为倒装芯片的基材，底部填充材料的研发大大地加快了。为了延缓焊点的应力疲劳，较大的基材和芯片硅片材料间的热膨胀差异使得底部填充剂的应用成为必然．而在底部填充材料和芯片接合界面的分层及底部填充剂中的空洞是触发许多芯片产生问题的根本原因之一。本篇将要讨论的是减少底部填充剂中的空洞的一些方法．[编者按]     

倒装芯片制造过程中非流动型底部填充剂的工艺参数

贴片前涂敷非流动型底部填充剂，既消除了免清洗焊剂残留物所带来的可靠性问题，又减少甚至根除了密封剂的固化时间，提高了生产效率。当然，为实现其优质工艺，必须对底充胶涂敷、贴片以及组件再流焊等因素予以认真考虑。     

倒装片可修复底部填充材料的研究现状及发展

有机基板上的倒装芯片一般采用底部填充技术以提高其封装的可靠性.有缺陷的芯片在倒装后难以进行返工替换,使得倒装芯片技术成本提高,限制了此技术的应用.提出新型可修复底部填充材料的开发成为解决这一问题的有效途径.介绍了倒装芯片的可修复底部填充技术和可应用于可修复底部填充材料的技术要求,并综述了国内外对于可修复底部填充材料的研究现状.     

底部填充工艺探讨

底部填充工艺是倒装芯片封装过程中的一个必不可少而且很关键的组成部分,底部填充工艺的成败将直接影响到封装的可靠性。本文针对底部填充工艺中需考虑的多个方面,如分配模式、胶水体积计算、硬件选择等,阐述如何改进工艺,增强底部填充的自动生产的能力。     

面向窄节距倒装互连的预成型底部填充技术

近年来随着电子产品的小型化发展,窄节距倒装芯片互连已经成为研究热点。传统的倒装芯片组装后底部填充技术(例如底部毛细填充)在用于窄节距互连时易产生孔洞,导致可靠性降低,因此产业界开发了面向窄节距倒装芯片互连的预成型底部填充技术,主要包括非流动底部填充和圆片级底部填充。介绍了这类新型底部填充技术的具体工艺及材料需求,并提出了目前其在大规模量产以及未来更窄节距应用中存在的问题及挑战,总结了目前产业界在提高量产生产效率、提升电互连的可靠性以及开发纳米级高热导率填料等方面提出的解决方案,分析了该技术未来的发展方向。     

基于表面能理论的倒装芯片封装下填充流动研究

为了预测倒装芯片封装中的下填充过程,通常要首先通过繁复的方法来求解平均毛细压.为了避免此问题,从能量的角度分析了倒装芯片封装工艺中的下填充流动过程.认为下填充是较低表面能的界面代替较高表面能的界面的过程,所释放的表面能用于形成流体流动的动能和克服阻力的能量损耗,期间能量守恒.在此分析的基础上建立了下填充流动的新模型.建立了可视化的下填充流动实验装置,并用下填充实验验证了所建立新模型的准确性.该模型避免了计算平均毛细压的复杂过程,并可方便地扩展到焊球排布形式不同的倒装芯片.     

底部填充技术的SMT应用研究

如BGA、CSP等倒装芯片的SMT应用越来越普遍,底部填充胶水可以有效提高倒装芯片焊点的机械强度,以避免因热循环应力疲劳或机械冲击力而产生的失效。本文详细描述了底部填充技术的SMT应用细节,包括底部填充胶水介绍、PCB DFM设计、涂胶前准备、涂胶过程和注意事项、涂胶设备介绍等。     

焊球正六边形排布倒装芯片的下填充毛细压研究

除了正四边形,正六边形也是倒装芯片中可行的焊球排布形式,为了预测封装倒装芯片时的下填充过程,需要精确计算毛细驱动压.在已有的焊球正四边形排布情况下平均毛细压计算方法的基础上,进一步研究了焊球正六边形排布情况下平均毛细压计算模型.通过分阶段处理,并根据质量守恒和力平衡的原则,分析了下填充过程,重点分析了填充面积和接触线跳跃量的计算,进而得到了计算平均毛细压的数学模型.通过实例验证了该模型的准确性,从而完善了倒装芯片封装工艺中的下填充流动解析模型.     

Study of Intermetallic Growth and Kinetics in Fine-Pitch Lead-Free Solder Bumps for Next-Generation Flip-Chip Assemblies

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 μm to 150 μm. With this reduction in pitch size, and thus in bump height and diameter, the interaction between die pad metallurgy and substrate pad metallurgy becomes more critical due to the shorter diffusion path and greater stress. Existing literature has not addressed such metallurgical interaction in actual fine-pitch flip-chip assemblies. This work studies intermetallic growth and kinetics in fine-pitch lead-free solder bumps through thermal aging of flip-chip assemblies. Based on this study, it is seen that Ni from the die pad diffuses to the substrate pad region and Cu from the substrate pad diffuses to the die pad region, thus the resulting intermetallic compounds at the die and substrate pad regions are influenced by the other pad as well. Such cross-pad interaction is much stronger in fine-pitch solder bumps with smaller standoff height. It is seen that the die pad region contains Ni₃P and (Cu,Ni)₆Sn₅ after thermal aging, while the substrate pad region contains Cu₃Sn and (Cu,Ni)₆Sn₅. By digitally measuring the thickness of the interfacial phases, the kinetics parameters and the activation energy were calculated for the growth of (Cu,Ni)₆Sn₅ on the substrate side. The Cu diffusion coefficient through the intermetallic compound (IMC) layer was found to be 0.03370 μm²/h, 0.1423 μm²/h, and 0.4463 μm²/h at 100°C, 125°C, and 150°C, respectively, and the apparent activation energy for the growth of compound layers was 67.89 kJ/mol.     

倒装芯片下填充流动二维化数值分析方法的应用

下填充流动是确保倒装芯片可靠性的重要封装工艺,其流场和流动过程具有明显的二维特征,通过降维得到的二维化数值分析新方法能高效地模拟下填充流动过程.针对一种焊球非均匀、非满布的典型倒装芯片,用该数值分析方法模拟了单边下填充流动的过程,并用实验对模拟结果进行了检验.实验采用了可视化的下填充流动装置,倒装芯片试样采用硅-玻璃键合(SOG)方法制作.将数值模拟结果与实验结果比较发现,无论是流动速度还是流动前沿的形态,两者均呈现出较高的吻合度.这表明:针对下填充流动的二维化数值分析方法兼具高效性和准确性,具有较高的应用价值.     

Numerical Modeling for the Underfill Flow in Flip-Chip Packaging

In the prediction of underfill flow in a flip-chip package, numerical methods are usually used for flow analysis and simulation since analytical methods cannot meet the requirement for predicting fluid distribution in a planar analysis. At present, there appears to be no simulation software commercially available that is able to provide adequate prediction for the underfill flow process driven by capillary force in a micro-cavity situation. In the study presented in this paper, a numerical model was proposed for the prediction of flip-chip underfill flow. In this model, the power-law constitutive equation was used to describe the non-Newtonian behavior of encapsulant fluids and a time-dependent velocity boundary condition was used instead of the pressure boundary condition commonly used. The comparison between the model-predicted and experimental results indicated that this model can give a good prediction for the underfill flow in a micro-cavity. This model was implemented by a general-purpose commercially available software program ANSYS, which has a high reliability and wide accessibility.      

焊料凸点回流时的桥接现象研究

在用回流焊料凸点时,常会发生凸点的桥接现象,致使芯片报废。此时,相邻的多个凸点彼此融合,聚集成一个更大的焊料球,并吸干先前各凸点中的焊料。本文研究了电镀PbSn凸点和蒸发铟凸点的回流过程中出现的桥接现象。介绍了桥接现象产生的过程及其背景,分析了桥接现象的机理,提出了改进措施。     

An Analytical Model for Predicting the Underfill Flow Characteristics in Flip-Chip Encapsulation

This article describes an analytical model for the prediction of the underfill flow characteristics in a flip-chip package driven by capillary action. In this model, we consider non-Newtonian fluid properties of the encapsulant as opposed to most other studies where Newtonian fluid properties were assumed for the underfill flow. The power-law constitutive equation was applied in our study. The simulation based on this model agreed well with the measurement obtained from the experiments available in literature. It was further shown that this model performs better than the Washburn model traditionally used for the prediction of underfill flow characteristics in the flip-chip packaging. Based on this model, the effects of the solder bump pattern (including bump pitch, solder bump diameter, and gap height) on the process variables (i.e., flow front and filling time) were studied, which facilitated both the package design and the process optimization.     

Effect of Metal Bond-Pad Configurations on the Solder Microstructure Development of Flip-Chip Solder Joints

Various microstructural zones were observed in the solidified solder of flip-chip solder joints with three metal bond-pad configurations (Cu/Sn/Cu, Ni/Sn/Cu, and Cu/Sn/Ni). The developed microstructures of the solidified flip-chip solder joints were strongly related to the associated metal bond pad. A hypoeutectic microstructure always developed near the Ni bond pad, and a eutectic or hypereutectic microstructure formed near the Cu pad. The effect of the metal bond pads on the solder microstructure alters the Cu solubility in the molten solder. The Cu content (solubility) in the molten Sn(Cu) solder eventually leads to the development of particular microstructures. In addition to the effect of the associated metal bond pads, the developed microstructure of the flip-chip solder joint depends on the configuration of the metal bond pads. A hypereutectic microstructure formed near the bottom Cu pad, and a eutectic microstructure formed near the top Cu pad. Directional cooling in the flip-chip solder joint during the solidification process causes the effects of the metal bond-pad configuration. Directional cooling causes the Cu content to vary in the liquid Sn(Cu) phase, resulting in the formation of distinct microstructural zones in the developed microstructure of the flip-chip solder joint.     

固化残余应力对倒装焊底充胶可靠性的影响

通过对考虑固化过程影响的倒装焊底充胶的热－机械有限元模拟，分析了底充胶在固化过程中因体积收缩，材料的刚度增加及受周围材料的约束所产生的固化残余应力对随后热循环加载下底充胶应力分布与幅值的影响，得出了固化过程及其固化残余应力不但进一步劣化了热循环加载下底充胶中的应力值，而且还影响了随后底充胶的热－机械疲劳可靠性的结论。     

分步电镀法制备Sn-Ag-In三元凸点及其可靠性

本文介绍了一种制备细节距、元素分布均匀的Sn-Ag-In三元凸点的方法。其特征在于在Cu凸点下金属层上分步电镀Sn-Ag和In,通过精确控制回流过程,获得了Sn1.8Ag9.4In凸点。研究发现位于Sn-Ag-In焊料和Cu之间的金属间化合物厚度随回流时间的延长而生长,这使得焊料基体中Ag相对浓度增加,因此在凝固过程中,更多的Ag2In相析出,起到了颗粒增强的作用。