3D堆叠封装硅通孔结构的电-热-结构耦合分析

硅通孔(TSV)技术作为三维封装的关键技术,其可靠性问题受到广泛的关注。基于ANSYS平台,通过有限元方法,对3D堆叠封装的TSV模型进行了电-热-结构耦合分析,并进一步研究了不同的通孔直径、通孔高度以及介质隔离层SiO_2厚度对TSV通孔的电流密度、温度场及热应力分布的影响。结果表明:在TSV/微凸点界面的拐角处存在较大的电流密度和等效应力,容易引起TSV结构的失效;增大通孔直径、减小通孔长度可以提高TSV结构的电-热-机械可靠性;随着SiO_2层厚度的增加,通孔的最大电流密度增大而最大等效应力减小,需要综合考虑合理选择SiO_2层厚度。     

基于热-流-力耦合计算的多芯片组件布局构形优化

基于构形理论和多物理场耦合数值计算方法,建立了自然对流条件下均匀产热的多芯片组件模型,给定印刷电路板面积和芯片总占地面积为约束条件,分别以最高温度、最大应力和最大形变为优化目标,以芯片个数及芯片长宽比为设计变量,研究了芯片布局演化对系统性能的影响.结果 表明:不同优化目标下,最优构形均为芯片长宽比为2.1的8芯片布局方式,多芯片组件的最高温度、最大应力和最大形变分别最多可降低16.5％,28.3％和26.9％.对芯片个数和芯片长宽比双自由度的优化效果要明显优于仅对芯片长宽比的单自由度优化.     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

用于3D WLP和3D SIC的穿透硅通孔技术

数家研究小组和公司已经展示了通过芯片叠层和穿透硅通孔（TSV）互连来实现复杂3D芯片的可行性。     

3DIC集成与硅通孔(TSV)互连

介绍了3维封装及其互连技术的研究与开发现状,重点讨论了垂直互连的硅通孔（TSV）互连工艺的关键技术及其加工设备面临的挑战．提出了工艺和设备开发商的应对措施并探讨了3DTSV封装技术的应用前景。     

3D封装与硅通孔(TSV)工艺技术

在IC制造技术受到物理极限挑战的今天,3D封装技术越来越成为了微电子行业关注的热点。对3D封装技术结构特点、主流多层基板技术分类及其常见键合技术的发展作了论述,对过去几年国际上硅通孔（TSV）技术发展动态给与了重点的关注。尤其就硅通孔关键工艺技术如硅片减薄技术、通孔制造技术和键合技术等做了较详细介绍。同时展望了在强大需求牵引下2015年前后国际硅通孔技术进步的蓝图。     

空心硅通孔的设计及其传输性能

硅通孔(TSV)能够实现信号的垂直传输,是微系统三维集成中的关键技术,在微波毫米波领域,硅通孔的高频传输特性成为研究的重点。针对微系统三维集成中,无源集成的硅基转接板的空心TSV垂直传输结构低损耗的传输要求,进行硅通孔的互连设计和传输性能分析。采用传输线校准方式,首先在硅基转接板上设计TSV阵列接地的共面波导(CPW)传输线和带TSV过孔的传输结构,并分别进行仿真分析,计算得出带TSV过孔的传输结构的插入损耗;然后通过后道TSV工艺,在硅基转接板上制作传输线和带TSV过孔的传输结构,用矢量网络分析仪法测试传输线和带TSV过孔的传输结构的插入损耗;最后计算得到单个TSV过孔的插入损耗,结果显示在0.1～30 GHz频段内其插入损耗S21≤0.1 dB,实现了基于TSV的低损耗信号传输。     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

硅通孔(TSV)转接板微组装技术研究进展

以硅通孔(TSV)为核心的三维集成技术是半导体工业界近几年的研发热点,特别是2.5D TSV转接板技术的出现,为实现低成本小尺寸芯片系统封装替代高成本系统芯片(So C)提供了解决方案。转接板作为中介层,实现芯片和芯片、芯片与基板之间的三维互连,降低了系统芯片制作成本和功耗。在基于TSV转接板的三维封装结构中,新型封装结构及封装材料的引入,大尺寸、高功率芯片和小尺寸、细节距微凸点的应用,都为转接板的微组装工艺及其可靠性带来了巨大挑战。综述了TSV转接板微组装的研究现状,及在转接板翘曲、芯片与转接板的精确对准、微组装相关材料、工艺选择等方面面临的关键问题和研究进展。     

三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

Scheduling Tests for 3D Stacked Chips under Power Constraints

This paper addresses Test Application Time (TAT) reduction under power constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the test flow for 3D TSV-SICs is yet undefined. In this paper we present a cost model to find the optimal test flow. For the optimal test flow, we propose test scheduling algorithms that take the particulars of 3D TSV-SICs into account. A key challenge in testing 3D TSV-SICs is to reduce the TAT by co-optimizing the wafer sort and the package test while meeting power constraints. We consider a system of chips with cores that are accessed through an on-chip JTAG infrastructure and propose a test scheduling approach to reduce TAT while considering resource conflicts and meeting the power constraints. Depending on the test schedule, the JTAG interconnect lines that are required can be shared to test several cores. This is taken into account in experiments with an implementation of the proposed scheduling approach. The results show significant savings in TAT.     

Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

Thermal stress issues in a three-dimensional (3D) stacked wafer system were examined using finite-element analysis of the stacked wafers. This paper elucidates the effects of the bonding dimensions on mechanical failure and the keep-away zone, where devices cannot be located because of the stress in the Si. The key factors in decreasing the thermal strain were the bonding diameter and thickness. When the bonding diameter decreased from 40 μm to 12 μm, the equivalent strain decreased by 83%. It is noteworthy that the keep-away zone also decreased from 17 μm to zero when the bonding diameter decreased from 40 μm to 12 μm. When the bonding thickness doubled, the equivalent strain decreased by 44%. The effects of the dimensions and arrangement of through-silicon vias (TSV) were also analyzed. Small TSV diameter and pitch are important to decrease the equivalent strain, especially when the amount of Cu per unit volume is fixed. When the TSV diameter and pitch decreased fourfold, the equivalent strain decreased by 70%. The effects of TSV height and the number of die stacks were not significant, because the underfill acted as a buffer against thermal strain.     

Design and Fabrication of a Flip-Chip-on-Chip 3-D Packaging Structure With a Through-Silicon Via for Underfill Dispensing

This paper presents a new package design for multichip modules. The developed package has a flip-chip-on-chip structure. Four chips [simulating dynamic random access memory (DRAM) chips for demonstration purpose] are assembled on a silicon chip carrier with eutectic solder joints. The I/Os of the four chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. A through-silicon via (TSV) hole is made at the center of the silicon chip carrier for optional underfill dispensing. The whole multichip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly and X-ray inspection, the underfill process is applied to some selected specimens for comparative study purpose. The underfill material is dispensed through the center TSV hole on the silicon chip carrier to encapsulate the solder joints and the four smaller chips. Subsequently, scanning acoustic microscopy (SAM) is performed to inspect the quality of underfill. After the board-level assembly, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of all specimens is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1200 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, instead of solder joints. The features and merits of the present package design are discussed in details in this paper.     

硅通孔尺寸与材料对热应力的影响

通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。     

Through-Silicon via Interconnection for 3D Integration Using Room-Temperature Bonding

One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a “mechanical-caulking” technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured. However, a customized design, assuming TSV interconnections in the existing MCU, needs to be introduced for practical use to achieve ${rm SiO}_{2}$ etching with shorter turn around time (TATs) and high TSV yields of more than 99%.      

3G时代 从“芯”来看

本文探讨了3G终端对应用处理器和多媒体处理芯片产品的技术需求及解决方案.