一种适于FPGA芯片的SRAM单元及外围电路设计

静态存储器(SRAM)功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。     

一种测试SRAM失效的新型March算法

随着工艺偏差的日益增加,新的失效机制也在亚100 nm工艺的CMOS电路里出现了,特别是SRAM单元。SRAM单元的故障由晶体管阈值电压Vt差异引起,而Vt差异又是由工艺偏差造成的。对于这类SRAM失效机制,需要把它映射成逻辑故障模型,并为检测出这类故障研究出新的March测试序列。针对这些逻辑故障模型,提出了一种新型的March算法序列;并通过验证,得到了很高的测试覆盖率。     

一种提高SRAM写能力的自适应负位线电路设计

随着器件尺寸缩小到纳米级,在SRAM生产过程中,工艺偏差变大会导致SRAM单元写能力变差.针对这一问题,提出了一种新型负位线电路,可以提高SRAM单元的写能力,并通过控制时序和下拉管的栅极电压达到自我调节负位线电压,使负电压被控制在一定范围内.本设计采用TSMC 40nm工艺模型对设计的电路进行仿真验证,结果证明,设计的电路可以改善写能力,使SRAM在电压降到0.66V的时候仍能正常工作,并且和传统设计相比,本电路产生的负电压被控制在一个范围内,有利于提高晶体管的使用寿命,改善良率,节省功耗.     

IMEC验证FinFET优势22纳米及以下节点FinFET或是必须选择

IMEC研究机构比较了一种平面晶体管以及两种FinFET垂直结构晶体管,测试其在尺寸微缩能力以及工艺变差控制方面的表现。参与比较的是分别基于三种晶体管结构的六晶体管SRAM单元及阵列。IMEC由此得出的结论是,对SRAM类产品来说,FinFET器件在工艺变差控制方面以及产品良率方面要优于平面结构CMOS。     

板上驱动封装LED的电源IC失效分析

通过基础电性测试确认了板上驱动（DOB）封装LED光源的失效现象,通过X射线无损探测内部的结构,得到了基本电路结构原理图。分别对LED光源电路上的各个分立部分做示波器测试,确认了失效部位为电源IC。通过物理开封并结合扫描电子显微镜（SEM）、聚焦离子束显微镜（FIB-SEM）和能谱仪（EDS）测试,分析出该LED光源亮度下降的根本原因是电源IC异常。而该电源IC失效的原因为Fe元素残留与污染引发蚀刻异常,含Fe元素异物镶嵌在芯片内部,导致芯片内部蚀刻线路异常,造成内部功能单元失效,最终使IC功能偏离设计,局部或全部失效。     

用于双极电路ESD保护的SCR结构设计失效分析

针对目前双极电路的ESD保护需求,引入SCR结构对芯片进行双极电路ESD保护。通过一次流片测试,发现加入SCR结构的电路芯片失效,SCR结构的I-V特性曲线未达到要求。从设计问题和工艺偏差两方面入手,分析了失效原因,通过模拟仿真,验证了失效是因为在版图设计时为节省版图面积,将结构P阱中NEMIT扩散区域边上用来箝位的电极开孔去掉造成的,并非工艺偏差导致的。通过二次流片测试,验证了失效原因分析的正确性,SCR器件结构抗ESD电压大于6kV,很好地满足了设计要求。     

一种新的基于SRAM的快速综合技术

对静态随机存储器(SRAM)全定制设计过程中的版图设计工作量大、重复性强的问题进行了分析,并在此基础上提出了一种新的应用于SRAM设计的快速综合技术。这种技术充分利用SRAM电路重复单元多的特点,在设计过程中尽可能把电路版图的硬件设计转换为使用软件来实现,节省了大量的版图设计和验证的时间,从而提高了工作效率。这种技术在龙芯Ⅱ号CPU的SRAM设计中得到了应用;芯片采用的是中芯国际0.18μm CM O S工艺。流片验证表明,该技术对于大容量的SRAM设计是较为准确而且有效的。     

抗单粒子翻转效应的SRAM研究与设计

在空间应用和核辐射环境中,单粒子翻转(SEU)效应严重影响SRAM的可靠性。采用错误检测与校正(EDAC)和版图设计加固技术研究和设计了一款抗辐射SRAM芯片,以提高SRAM的抗单粒子翻转效应能力。内置的EDAC模块不仅实现了对存储数据"纠一检二"的功能,其附加的存储数据错误标志位还简化了SRAM的测试方案。通过SRAM原型芯片的流片和测试,验证了EDAC电路的功能。与三模冗余技术相比,所设计的抗辐射SRAM芯片具有面积小、集成度高以及低功耗等优点。     

评测千兆以太网性能的线缆性能测试仪

瑞萨科技公司开发出一种有助于采用65nm制造工艺生产的SRAM（静态随机存取存储器）实现稳定运行的技术。新技术采用了一种直接图形成型布局和读辅助及写辅助电路，以克服采用精细特征工艺技术时由于晶体管固有特性可变性带来的SRAM不稳定问题。采用65nm工艺的存储单元测试芯片包含一个8MB6晶体管型SRAM，利用该芯片对稳定运行能力进行了验证。测试数据显示，利用这种设计方法可以在大批量生产时实现宽泛的整体Vth的可变性——与不采用该方法的情况相比产量可提高两倍以上。其应用包括用于微处理器和系统级芯片（SoC）器件的嵌入式SRAM。     

单片集成TFT-LCD驱动芯片内置SRAM验证技术研究

介绍了TFT-LCD驱动芯片内置SRAM验证方法:(1)采用模拟验证和形式验证相结合的前端设计验证方法,完成各模块的功能验证及整个SRAM的功能和时序验证.模拟验证技术,利用模拟工具对被测试模块施加测试激励信号,检查输出信号是否符合预期要求;模拟方法可以同时检查被测试模块的功能及时序方面的响应情况,能够全面体现电路的行为.形式验证技术,在集成电路设计中,是通过算法的手段进行等价性检查,比较两种设计之间的功能等价性.(2)采用结构化抽取寄生参数和建立关键路径的方法,完成SRAM性能的评估,即后端设计验证.并且用具体实例详细描述了以上方法在电路仿真验证中的应用,并给出了部分电路结构及仿真结果,进一步论述了该方法的可行性及实用性.     

Failure analyses for debug and ramp-up of modern IC’s

Quick and successful failure analysis is a key component for in-time realization and ramp-up of new products. The structure of analysis flow from verification of failure to fault identification and corrective actions is presented with the focus on modem techniques in fault localization. For the area of design debug techniques for internal probing and circuit modification by mask less redesign are described, yield learning is demonstrated on the example of SRAM fails and scan shift loss. Finally an assessment of the future of failure analysis in this field is given.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

抗辐射128kb PDSOI静态随机存储器

介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验.     

Correlation between predicted cause of SRAM failures and in-line defect data

A correlation has been made between the bitmap data from an SRAM and the in-line defect data as measured on a KLA2122 and Tencor7700. The SRAM was a dedicated design for yield enhancement in a 0.35 μm technology. Extra design features were added to encourage the change of having defect on particular places and discourage it on safe designed places. From the failure signature of a memory cell (0 or 1) and its failure extent (single cell, double cell, bitline, wordline (WL), …) one can predict the process-related cause of the failure. A special test program has been written which translates the electrical data from the failing cells into its process defect.The failing bits from the SRAM have been transferred into a KLA results file and added as an extra inspection to the defect database. With a defect source analysis it was possible to find out if the electrical failing bits were seen as a defect in the line and at which steps. With this analysis it is possible to find out if the predicted cause of the process defects from the test program is confirmed by the performed in-line inspections. With an intensive inspection plan about half of the electrical defects were seen in the line. For a large amount of these defects their predicted cause are indeed matching with the inspected layer. Moreover, quite some unknown failures can be explained by the in-line inspections. This correlation work makes it possible to prioritize in tackling the most killing defect sources.     

超声波清洗引入的芯片金属化裂纹机理分析

对某塑封器件进行破坏性物理分析(DPA),发现芯片表面存在玻璃钝化层裂纹和金属化层划伤的缺陷。对缺陷部位进行扫描电子显微镜(SEM)检查和能谱(EDS)分析,通过形貌和成分判断其形成原因为开封后的超声波清洗过程中,超声波振荡导致环氧塑封料中的二氧化硅填充颗粒碰撞挤压芯片表面,从而产生裂纹。最后,进行了相关的验证试验。研究结论对塑封器件的开封方法提出了改进措施,对塑封器件的DPA检测及失效分析(FA)有一定借鉴意义。     

An interactive VLSI CAD tool for yield estimation

The yield of a VLSI chip depends on the sensitivity of the chip to defects occurring during the fabrication process, among other factors. To predict this sensitivity, one usually needs to compute the so-called critical area (A_c), which reflects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A_c efficiently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm that will solve it efficiently. This paper provides an interactive, accurate, and fast method for the evaluation of critical area as a design tool; the tool utilizes good visual feedback to allow layout improvement for higher yield. The algorithm is compared to other yield-prediction methods, which use either the Monte Carlo approach (VLASIC) or a deterministic approach (SCA); the algorithm is shown to be faster. It also has the advantage that it can graphically show a detailed `defect sensitivity map' that can assist a chip designer in improving the yield of his/her layout     

Localization and physical analysis of a complex SRAM failure in 90nm technology

In this paper the analysis process of a complex SRAM failure in 90nm technology is introduced in detail. Using a correlation method, it could be traced back to a failure with an increased supply current. With the help of MCT emission microscopy and thermal laser stimulation (TLS) the defects were localized at both edges of every failing SRAM block. Further inspection by passive voltage contrast (PVC) and atomic force prober (AFP) current imaging led to a localization down to contact level. In the TEM analysis high angle annular dark field scanning TEM (HAADF STEM) was used to obtain better material contrast. CoSi residues were found at the wall of spacers of the failing FETs. Further surface parallel TEM inspection confirmed the hypothesis of a new type of bridging defect, i.e. CoSi stringers along word lines in SRAM cells, which has not been observed before to our knowledge. The process adjustment in the fab to avoid this failure led to a significant yield improvement. The abstract should be 75-200 words long, summarizing the work and placing it in an appropriate context.     

SRAM的高成品率优化设计技术

提出了一种嵌入式SRAM的高成品率优化方法:通过增加冗余逻辑和电熔丝盒来代替SRAM中的错误单元。利用二项分布计算最大概率缺陷字数,从而求出最佳冗余逻辑。将优化的SR SRAM64 K×32应用到SoC中,并对SR SRAM64K×32的测试方法进行了讨论。该SoC经90 nm CMOS工艺成功流片,芯片面积为5.6 mm×5.6 mm,功耗为1997 mW。测试结果表明:优化的SR SRAM64 K×32在每个晶圆上的成品数增加了191个,其成品率提高了13.255%。     

90nm CMOS工艺SRAM的优化及应用

提出了一种优化的SRAM,它的功耗较低而且能够自我修复.为了提高每个晶圆上的SRAM成品率,给SRAM增加冗余逻辑和E-FUSE box从而构成SR SRAM.为了降低功耗,将电源开启/关闭状态及隔离逻辑引入SR SRAM从而构成LPSR SRAM.将优化的LPSR SRAM64K×32应用到SoC中,并对LPSR SRAM64K×32的测试方法进行了讨论.该SoC经90nm CMOS工艺成功流片,芯片面积为5.6mm×5.6mm,功耗为1997mW.测试结果表明:LPSR SRAM64K×32功耗降低了17.301%,每个晶圆上的LPSRSRAM64K×32成晶率提高了13.255%.