一种精确测量MOSFET晶圆导通电阻的方法

导通电阻的准确测量是低导通电阻MOSFET晶圆测试中的一个难点。要实现毫欧级导通电阻的测试,必须用开尔文测试法;但实际的MOSFET晶圆表面只有两个电极(G、S),另外一个电极(D)在圆片的背面,通常只能将开尔文的短接点接在承载圆片的吸盘边缘,无法做到真正的开尔文连接,由于吸盘接触电阻无法补偿而且变化没有规律,导致导通电阻无法精确测量。介绍了一种借用临近管芯实现真正开尔文测试的方法,可以实现MOSFET晶圆毫欧级导通电阻准确稳定的测量。     

基于ABM器件的SiC MOSFET建模研究

针对不同温度下SiC MOSFET模型精度不足的问题,提出一种基于模拟行为模型(ABM)器件建立SiC MOSFET模型的方法.分别对整体模型的沟道电流、导通电阻和栅漏电容部分进行改进,引入了阈值电压和跨导系数的温度调节函数,考虑了温度和栅源电压对导通电阻的影响,提出了无开关栅漏电容,建立了满足连续温度仿真的SiC M...     

电源管理

英飞凌推出兼具超结技术和传统高压器件优势的MOSFET英飞凌科技股份公司推出下一代高性能金属氧化物半导体场效应晶体管(MOSFET)600V CoolMOS C6系列。有了600V CoolMOS C6系列器件,诸如PFC(功率因数校正)级或PWM(脉宽调制)级等能源转换产品的能源效率可得到大幅提升。全新C6技术融合了现代超结结构及包括超低单位面积导通电阻(例如采用TO-220封装,电阻仅为99毫欧)     

低压沟槽功率MOSFET导通电阻的最优化设计

研究了低压沟槽功率MOSFET(<100V)在不同耐压下导通电阻最优化设计的差别。给出了确定不同耐压MOSFET参数的方法,简要分析了沟槽MOSFET的导通电阻;利用Sentaurus软件对器件的电性能进行模拟仿真。理论和仿真结果均表明,耐压高的沟槽MOSFET的导通电阻比耐压低的沟槽MOSFET更接近理想导通电阻,并且,最优导通电阻和最优沟槽宽度随着耐压的提高而逐渐增大。     

基于双核架构的全电子引信测试仪设计

传统的全电子引信无源导通电阻测试均采用外接电阻测试设备或通用的导通电阻测试电路设计,与全电子引信通电工作的电气性能测试毫无关联,无法避免故障产品加电后烧毁的风险。为此提出了能对无源导通电阻和全电子引信通电工作电气性能综合诊断的系统性设计思路,设计了一种基于ARM芯片和FPGA双核架构的全自动测试控制架构和24 bit高精确度四线制无源导通电阻测试电路,对全电子引信的对外接口部分的无源导通电阻及引信加电工作特性进行全面测试。测试结果表明,该设计能够进行无源导通电阻高精确度测试及通电后工作性能的综合测试,电阻测量精确度为±0.1%。     

30 V UMOS中影响导通电阻平坦度的因素分析

功率MOSFET作为开关器件时,导通电阻的平坦度是衡量其性能的重要参数。研究影响导通电阻平坦度的因素,并对其进行优化,有助于改善器件的性能。低压UMOS中,沟道电阻是导通电阻的主要部分。文章以沟道电阻为分析对象,利用公式分析影响因素,通过Sentaurus TCAD仿真验证了导通电阻平坦度的变化趋势。通过改变P型基区离子注入剂量和栅氧层厚度进行仿真。仿真结果表明,通过减小栅氧层厚度和减少P型基区注入剂量,可获得较好的导通电阻平坦度。     

MOSFET继电器G3VM-21LR10

G3VM-21LR10是0MRON公司的产品,它是由红外发光二极管及光触发MOSFET组成的光电式继电器。与一般电磁式继电器相比较,光电式继电器尺寸很小（是贴片式的）、工作电流很小、通或断的响应时间快、工作温度范围宽、耐振动性能好。但由于它由MOSFET的导通时存在导通电阻（R陷。㈨）3Q左右,所以它的导通电阻比电磁式触头的接触电阻要大。     

元器件与组件

新型电子烟火启动器特殊薄膜电阻芯片;具有超低导通电阻的P沟道MOSFET;超低电容高分子ESD保护元件;新型家电用高可靠性压敏电阻器。     

英飞凌30V车用MOSFET具备全球最低通态电阻

英飞凌科技股份公司近日面向大电流应用的汽车推出一款具备全球最低通态电阻的30V功率MOSFET（金属氧化物半导体场效应晶体管）。全新的OptiMOS—T230V MOSFET是一款N沟道器件,在10V栅源电压条件下,漏极电流为180A,而通态电阻仅为0．9毫欧。     

栅极电阻对GaN MOSFET瞬态特性的影响研究

为了研究栅极电阻对GaN MOSFET的开关速率和输出特性中出现振荡的影响,首先利用MOSFET的基本公式对其导通和关断时的输出瞬态电流进行了理论推导,然后通过实验平台测试GaN MOSFET的瞬态电流值,且与理论值对比,验证栅极电阻带来的影响。实验结果表明,GaN MOSFET的瞬态电流值实验值与理论值基本吻合,在导通和关断时,GaN MOSFET的输出瞬态电流和输出电流的高频震荡均随栅极电阻的增加而减小。栅极电阻从10 Ω变化到100 Ω时,导通时开关速率上升率占总开关速率上升率的84.7%,关断时开关速率下降率占总开关速率下降率的54.06%。在栅极电阻为10~100 Ω范围内,GaN MOSFET具有较快的开关速度。     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

Semisuperjunction MOSFETs: new design concept for lower on-resistance and softer reverse-recovery body diode

A new superjunction (SJ) structure offering remarkable advantages compared with the conventional SJ structure is proposed and demonstrated for a power-switching device. In the proposed structure (semi-SJ structure), an n-doped layer is connected to the bottom of the SJ structure. According to the results of experiment and simulation, the semi-SJ structure has both lower on-resistance and softer recovery of body diode than conventional SJ MOSFETs. The fabricated semi-SJ MOSFETs with breakdown voltage of 690 V realize on-resistance 28% lower than that of the conventional SJ MOSFET with same aspect ratio. The softness factor of the body diode is also improved by a factor of five. The proposed MOSFET is very attractive for H bridge topology applications, such as switching mode power supplies and small inverter systems, thanks to the low on-resistance and the soft recovery body diode.     

沟槽栅低压功率MOSFET的发展（上）——减小漏源通态电阻Rds（on）

近些年来,采用各种不同的沟槽栅结构使低压MOSFET功率开关的性能迅速提高。本文对该方面的新发展进行了论述。本文上篇着重于降低通态电阻Rds（on）方面的技术发展,下篇着重于降低优值FOM方面的技术发展。     

An on-chip ESD protection circuit with low trigger voltage inBiCMOS technology

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (~7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (~Ω). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (~80 V/μm width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips     

Model requirements for simulation of low-voltage MOSFET in automotive applications

This paper focuses on the modeling of low-voltage automotive power electronic circuits to obtain accurate system simulation, including estimation of losses. The aim is to compare several metal-oxide semiconductor field-effect transistor (MOSFET) models to find out which can be used for low-voltage, high-current automotive converter simulations. As these models are intended for system simulation, only analytical models are addressed as they may be implemented into any circuit simulator. The different modes of operation of the switches are described (commutation, synchronous rectification, avalanche...), and several models of the power MOSFET transistor, allowing for simulation in these modes, are presented. Special care is given to the parameter extraction methods and to the interconnection model of the commutation cell. The four test circuits used to identify the low-voltage power MOSFET model parameters are presented. Comparison between simulations and measurements obtained with a calorimeter are then detailed. This measurement method is accurate and offers a simple way to prove the quality of simulation results. It is shown that the parameter identification is of major concern to achieve high accuracy, as classical Spice models can give good results, providing the model parameters are correctly set.     

Online calibration of MOSFET on-state resistance for precise current sensing

An approach for online current sensing calibration is presented where an auxiliary switch and a precision sense resistor are connected in parallel with a main power switch to achieve accuracy comparable to the sense resistor method, together with the advantage of essentially no additional power loss. The proposed current-sensing circuit and the calibration methods are particularly well suited for digital controller implementations where the required control and calibration functions can be easily accomplished. Experimental results with a digitally controlled 1.5-V 15-A synchronous buck converter demonstrate functionality of the online calibration approach, showing a significant improvement in accuracy over voltage sensing across the power MOSFET on-resistance.     

低温下功率MOSFET的特性分析

文章完成了对功率MOSFET（Metal Oxide Semiconductor Field Effect Transistor）闽值电压和通态阻抗在77K-300K范围内的实验测试，并结合上述两个参数宽温区的数学模型进行了相应的分析．从实验结果中．我们发现阀值电压随温度的降低略有升高；而通态阻抗随温度的降低则下降得非常明显。通态阻抗是影响功率MOSFET开关损耗的重要参数，所以在低温下功率MOSFET的开关损耗将大幅度下降。     

Study of 90-nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

We report 90-nm MOSFET subthreshold hump characteristics obtained for the first time by using a newly developed MOSFET array test structure. The array contains small-scale device-under-test groups with a new poly-Si gate layout pattern, which eliminates the influence of gate leakage and off leakage currents observed on measured MOSFET parameter data such as Vth, Ion, and subthreshold slope. We confirmed that subthreshold humps occur at random in an array. The rate at which humps occur is expressed as a percentage with respect to the whole array (referred to as the hump occurrence rate); the rate depends on chips from a wafer. It is also confirmed that the influence of subthreshold humps on /spl sigma/(Vth) is not negligible, and we revealed that it is important to design RF/analog circuits with an appropriate current density to reduce their influence. By extracting hump variations using a MOSFET array, it is possible to accurately estimate and reduce the standby current in logic large-scale integration (LSI) chips.     

Estimation of fault-free leakage current using wafer-level spatial information

Leakage current or the I/sub DDQ/ test has been shown to be an effective test screen in combination with traditional test methods. However, leakage current is rising rapidly as semiconductor technology advances. This makes it difficult to distinguish between faulty and fault-free chips using traditional threshold setting methods. This paper presents a method to estimate leakage current using neighboring chip information on a wafer. Outlier chips are rejected, and a least-squares-fit plane through neighboring chips is used to estimate defect-free I/sub DDQ/. Chips that significantly deviate from the estimate are rejected. The proposed method is evaluated using industrial test data.     

Lateral power MOSFET for megahertz-frequency, high-density DC/DC converters

DC/DC converters to power future CPU cores mandate low-voltage power metal-oxide semiconductor field-effect transistors (MOSFETs) with ultra low on-resistance and gate charge. Conventional vertical trench MOSFETs cannot meet the challenge. In this paper, we introduce an alternative device solution, the large-area lateral power MOSFET with a unique metal interconnect scheme and a chip-scale package. We have designed and fabricated a family of lateral power MOSFETs including a sub-10 V class power MOSFET with a record-low R/sub DS(ON)/ of 1m/spl Omega/ at a gate voltage of 6V, approximately 50% of the lowest R/sub DS(ON)/ previously reported. The new device has a total gate charge Q/sub g/ of 22nC at 4.5V and a performance figures of merit of less than 30m/spl Omega/-nC, a 3/spl times/ improvement over the state of the art trench MOSFETs. This new MOSFET was used in a 100-W dc/dc converter as the synchronous rectifiers to achieve a 3.5-MHz pulse-width modulation switching frequency, 97%-99% efficiency, and a power density of 970W/in/sup 3/. The new lateral MOSEFT technology offers a viable solution for the next-generation, multimegahertz, high-density dc/dc converters for future CPU cores and many other high-performance power management applications.