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1.
王艳珍  王作辉  钟庆东 《广东化工》2012,39(10):62-63,48
粉体是ZnO压敏电阻制备的起点,粉料的混合均匀性直接影响压敏电阻的综合电性能。利用电位一电容法及Mott.Schottky分析并结合SEM扫描,探索ZnO压敏电阻粉体的均匀性与其电化学行为之间的关系。测试结果初步表明,ZnO压敏电阻粉体越均匀,电容越小,载流子浓度越小。  相似文献   

2.
本文论述了国外开发的几种片叠层压敏电阻的结构,特性及当前的发展方向,介绍了这类压敏电阻器在集成电路保护,汽车电路保护和CMOS器件保护等方面的应用。  相似文献   

3.
Varistor Behavior at Twin Boundaries in ZnO   总被引:4,自引:0,他引:4  
The electrical behavior of commercial ZnO varistor devices has been examined with voltage contrast microscopy and point contact dc electrical measurements. Nonlinear voltage-dependent behavior has been observed across both of the major crystalline boundary types present in the system: Bi2O3 layer containing ZnO grain boundaries (or grain boundaries) and antimony spinel layer internal ZnO inversion twin boundaries (or twin boundaries). Twin boundaries, which bisect practically every grain in a typical commercial device, possess potential barriers with higher average breakdown voltages than do grain boundaries. Certain zinc antimonate spinel (Zn7Sb2O12) grains are electrically isolated from the matrix, whereas others are conductive within the matrix.  相似文献   

4.
ZnO压敏电阻器的性能及发展   总被引:3,自引:0,他引:3  
简要回顾了ZnO压敏电阻器的历史,阐述了ZnO压敏电阻器的性能以及当前基础性研究的现状,并对其发展进行了展望。研究了Bi2O3和TiO2的掺杂对低压ZnO压敏电阻性能和微观结构的影响规律,从理论上分析了Bi2O3和TiO2添加剂的作用机理。为ZnO压敏电阻的低压化提供了理论依据和方法。  相似文献   

5.
The effects of sintering time and rate of cooling on the microstructure and current/voltage characteristics of a ZnO varistor material have been investigated. The results provide information about the development of microstructure during sintering and have been interpreted in terms of the role which microstructure plays in the determination of electrical properties. A continuous network of intergranular Bi2O3, which lies mainly along the triple junctions between ZnO grains, can give a substantial contribution to the leakage current. The conductivity of this skeleton depends upon its internal microstructure.  相似文献   

6.
7.
通过采用独特的Zn-Bi-Ti-Sn配方体系,并运用高温(800℃)烧银技术,可实现压敏电压低压化,并能很好解决低压极性问题。制得的产品其压敏场强约20V/mm左右,电压极性为1V以下,非线性系数大30以上,泄漏电流5μA以下,限制电压比约1.5(2.5A),芯片Φ10mm产品经1300A雷电流(8/20μS)冲击,压敏电压变化率为-3%左右,产品已实现产业化。  相似文献   

8.
We present a rare-earth-doped ZnO ceramic with nonohmic electrical properties. Analysis of the microstructure and composition indicates that the ceramic is composed of the main phase of ZnO and the second phase of rare-earth oxides (e.g., Dy2O3, Pr6O11, Pr2O3). The average grain size is markedly increased from 3 to 18 μm, with an increase in the sintering temperature from 1150° to 1350°C. The corresponding varistor voltage and nonlinear coefficient decrease from 1014 to 578 V/mm, and from 15.8 to 6.8, respectively. The resistivity of grain and grain boundary evaluated by the complex impedance spectrum indicates that the resistivity of the grain is approximately constant (∼103Ω), and the resistivity of the grain boundary decreases. The relative dielectric permittivity of the sintered ceramic samples is much larger than that of pure ZnO ceramic, which should be ascribed to the internal boundary layer capacitance effect.  相似文献   

9.
An atomistic simulation technique has been used to predict the spatial arrangement of the dopant species sodium, lithium, and chlorine within the zinc oxide lattice. The alkaline oxides are preferentially incorporated via a self-compensating mode, forming interstitial cations which hinder the migration of zinc interstitials and hence slow the degradation of the varistor. The addition of chloride ions is shown to negate this effect by forming sodium and chloride substitutional defects rather than any species involving sodium interstitial ions.  相似文献   

10.
在最高温度950℃、1050℃、1150℃、1250℃4个温度下,采用2种配方:98.3%ZnO-0.7%Bi2O3-1.0%TiO2(摩尔分数),相应的无TiO2配方99.3%ZnO-0.7%Bi2O3(摩尔分数),分别制备样品进行对比研究。发现前者在950℃和1050℃的烧结温度下,没有形成明显Bi2O3偏聚的晶界;在1150℃和1250℃下,却形成了清晰的富铋晶界。而后者在950℃、1050℃、1150℃、1250℃4个温度下均形成了非常明显且清晰可辨的ZnO晶粒和晶界。通过XRD及相对峰强分析,发现了Bi2O3和TiO2在低压ZnO压敏电阻中的相变过程,并对其在烧结过程中的作用提出新的解释。  相似文献   

11.
万帅  吕文中  付振晓 《硅酸盐学报》2012,40(4):523-524,525,526,527,528
用环境扫描电子显微镜(ESEM)、X射线衍射(XRD)和X射线能谱(EDXS)等研究了水基流延片式ZnO压敏电阻器的低温共烧工艺及其对微观结构和电学性能的影响规律。ESEM分析结果表明:当等静压压力为60 MPa时,Ag电极与流延膜生坯界面结合紧密,Ag电极分布连续,900℃共烧时,未出现开裂、分层,两者收缩率接近。EDXS和XRD分析结果表明:900℃共烧时,Ag在片式压敏电阻器中以单质形式存在,流延膜与Ag电极化学兼容性良好,且在共烧界面处未发现有明显的Ag离子扩散。该流延膜可以与Ag电极在900℃时实现低温共烧,用此制备的片式ZnO压敏电阻器具有良好的压敏性能:压敏电压V1mA=6.1 V,非线性系数α=28.1,漏电流IL=0.15μA。  相似文献   

12.
A ZnO varistors in series connected with a semi‐insulating GaAs photoconductive switches (SI‐GaAs PCSS's), a test method for ultrafast pulse response characteristics of ZnO varistor ceramics with DC bias was presented for the first time. The DC voltage distribution of the PCSS's and the varistors was measured in a dark state and the pulse response characteristics of the ZnO varistor ceramics was examined by a nanosecond laser pulse illuminating the PCSS's. The results indicate that the electric pulse output from the varistors includes capacitive current and conduction current and there is a time delay between their peaks. It is revealed that ZnO varistors has a nonlinear conductivity for the nanosecond electric impulse excitation and the barrier capacitance decay constant of the ceramics sample is 105 ns, which is explained through the analysis of examining the material structure and the conductive mechanisms.  相似文献   

13.
Penetration of a liquid (ZnO-PrO x ) into the grain boundaries of sintered, cobalt-doped ZnO pellets resulted in varistors with breakdown voltages per grain boundary in the 1-2 V range and nonlinearity coefficients of 22-37. The varistors were fabricated by spreading a thin layer of Pr6O11 powder paste on the surface of ZnO pellets and heating to various temperatures (1200°-1400°C) and times (0-60 min). Comparing the varistor properties per grain boundary (e.g., threshold voltage, donor concentration, and barrier height) of liquid penetration to those of conventional method indicated the individual grain boundaries were electrically activated when the samples were heat-treated above liquid-phase formation temperature.  相似文献   

14.
本文研究了分别掺杂微量Fe2O3杂质对ZnO压敏陶瓷的压敏特性的影响。研究结果表明:随Fe2O3掺杂量的增加,ZnO压敏陶瓷的压敏电压V1 mA和非线性系数先下降,后升高,最小值出现在Fe2O3摩尔掺杂量为1.00%;并从理论上详细地探讨了产生这些影响的原因。  相似文献   

15.
Co2O3的理化性能对ZnO压敏陶瓷电性能的影响   总被引:1,自引:0,他引:1  
本文详细研究了氧化钴的理化性能对ZnO压敏陶瓷性能的影响。论述了Co2O3的热特性对压敏陶瓷烧成工艺产生的影响及控制措施,从理论上探讨了氧化 中所含杂质Fe、Cu,Na等对ZnO压敏陶瓷电性能的不利作用。提出了控制的上限,并试制出一种用于氧化锌压敏陶瓷的性能优良的Co2O3粉体。  相似文献   

16.
Varistor Ceramics   总被引:23,自引:0,他引:23  
The development of varistor ceramics is reviewed with an emphasis on ZnO-based varistors formed by liquid-phase sintering. Particular attention is given to the effects of microstructural disorder on the properties of varistors and to the different modes of failure that can occur.  相似文献   

17.
本文对烧成后的掺TiO2低压ZnO压敏陶瓷进行了退火处理。测量了不同退火温度下ZnO陶瓷的压敏性能,运用XRD,SEM等分析方法研究了退火过程中ZnO陶瓷结构的变化。研究结果表明,退火过程中Ti^4+离子取代Zn^2+离子而固溶进入ZnO晶粒表面,是引起ZnO陶瓷压敏性能变化的主要原因,在退火温度不超过400℃时可获得较好的压敏性能。  相似文献   

18.
The doping of rare‐earth oxides can greatly improve the electrical characteristics of ZnO varistors. Thermally stimulated current (TSC) characteristic test, capacitance voltage (C–V) characteristic test, scanning electron microscope (SEM) test, and voltage current (V–I) test were carried out to study the influence of Y2O3 content on the electrical properties of ZnO varistors in this study. The results show that the grain size decreases while the voltage gradient increases as the Y2O3 content is increased. The reaction of Y2O3 with other additives leads to the decrease in grain‐boundary defects, which accounts for the decrement of barrier height, donor density, and surface state density. The trap level and trapped charge of ZnO varistors decrease as the Y2O3 content is increased from 0.3 to 0.9 mol%, which means the shallow traps inside ZnO varistors reduce, and the Y2O3 additive can greatly improve the TSC characteristic of ZnO varistors.  相似文献   

19.
以SnO2、Ta2O5和ZnO粉为原料,通过传统陶瓷固相反应烧结法制备了压敏变阻材料,实验中ZnO含量为0~2.00%(摩尔分数),烧结温度控制在1300~1500℃并保温2h。研究了ZnO掺杂量和烧结温度对材料的组成、微观结构和电学性能的影响。结果表明:在温度一定条件下,随着ZnO掺杂量的增加,材料的非线性系数、压敏电压先增大后减小;在ZnO含量一定时,随着烧结温度从1300℃升至1450℃,材料的非线性系数、压敏电压先增大后减小。ZnO掺杂量为0.50%时,在1450℃烧结得到的样品的非线性系数最高(6.2),漏电流最小(262vA/cm^2),压敏电压较高(83V/mm)。  相似文献   

20.
SnO2–Zn2SnO4 composite ceramics with a colossal dielectric permittivity and varistor behavior are prepared by traditional ceramic processing. By increasing bias voltage from 0 to 10 V at a low frequency (~103 Hz) and at room temperature, the relative permittivity decreased rapidly from about 20 000 to several thousand, whereas the radius of the semicircle in the complex impedance decreased and the tail gradually disappeared. However, the peak height and the position of the imaginary part of the complex modulus in the spectra were independent of the applied DC voltage. The slope deduced from the bias voltage‐dependent straight lines of the double‐logarithmic imaginary permittivity spectra were constant with a value of ?0.63 at high frequencies and they decreased to ?1 at low frequencies. The results strongly indicate that a number of weekly trapped charges existed in the ceramic bulk. From the temperature‐dependent dielectric and electric modulus spectra, the trapped charge activation energy was about 0.32 eV, which may be associated with the oxygen vacancies. Based on the results, a modified equivalent circuit related to the colossal dielectric permittivity and varistor properties was proposed, in which a Warburg impedance was added in parallel with the resistance and capacitance.  相似文献   

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