在基于LFSR重播种的压缩环境下同时降低测试数据量和测试功耗

集成电路测试中过高的测试功耗和日益增长的测试数据量是半导体工业面临的两大问题。本文提出了一种在基于线性反馈移位寄存器重播种的压缩环境下基于扫描块的测试向量编码方案。同时,本文也介绍了一种新颖的扫描块重聚类算法。本文的主要贡献是给出了一种灵活的测试应用框架,它能够极大地减少扫描移位期间的跳变个数和经由LFSR重播种生成的确定位的数目。因此,文中方案能够极大地降低测试功耗和测试数据量。在ISCAS’89基准电路上使用Mintest测试集进行的实验表明,本文方法能够减少72%-94%的跳变,并且能获得高达74%-94%的测试压缩率。     

采用基本门单元完全测试矢量的测试生成算法

文章介绍了一种采用基本逻辑门单元的安全测试矢量集生成测试矢量的方法，该方法可以将搜索空间限制在2(n 1）种组合内。它采用故障支配和故障等效的故障传播、回退等技术，建立了一套从局部到全局的测试生成新方法。同时，利用基本门单元安全测试矢量的规律性，可以实现最小的内存容量要求。在一些基准电路的应用实例中，得到了满意的结果。     

VLSI边界扫描测试故障诊断及其策略研究

介绍了支持JTAG标准的IC芯片结构和故障测试的4-wire串行总线,以及运用边界扫描故障诊断的原理.实验中分析了IC故障类型、一般故障诊断流程和进行扫描链本身完整性测试的方案,并提出了一种外加测试码向量生成的算法.该故障诊断策略通过两块xc9572 pc84芯片互连PCB板的实现方法进行验证,体现了该策略对于芯片故障定位准确、测试效率高、控制逻辑简便易行的优越性.     

并行折叠计数器的BIST方案

 本文提出了一种新的基于初始状态的并行折叠计数结构,并给出了建议的多扫描链的BIST方案.与国际上同类方法相比,该方案需要更少的测试数据存储容量、更短的测试应用时间,其平均测试应用时间是同类方案的0.265%,并且能很好地适用于传统的EDA设计流程.     

边界扫描技术在含DSP电路板测试与诊断的研究与应用

针对含DSP电路板的测试与诊断问题,本文提出一种利用边界扫描技术和传统的外部输入矢量测试相结合的方法,对含DSP电路板中的边界扫描器件的器件及非边界扫描器件进行了测试.测试结果表明:该测试方法对边界扫描器件及非边界扫描器件可进行有效的故障检测和故障隔离,并可将故障隔离至最小的测试单元.同时详细阐述了测试诊断方案、硬件设...     

数字电路测试向量自动生成系统的比较

把遗传算法与蚂蚁算法运用于组合电路向量自动生成系统,并比较两者性能的优劣,根据实验结果进一步提出优化组合方案,将此方案应用于同步时序电路的测试向量自动生成系统中。提出一种优化的数字电路的测试向量自动生成系统。这个系统集合了蚂蚁算法和遗传算法的优点,使系统能在更短时间生成更小的测试集,而又能达到原先的故障覆盖率。     

一种触摸式手持时间同步测试系统

本发明涉及时间同步检测系统技术领域,其特征在于:包括GPS/北斗信号接收定时单元,时间同步基准源单元,时间同步信号测试单元,时间同步信号仿真单元,网络化软件平台设计单元,LCD显示触摸控制单元和锂电池管理单元。本发明触摸手持时间同步测试系统在于结构设计轻巧,便于携带,触摸式控制,操作简单,为智能变电站中设备进行时间测试提供了有效的解决方案,有效增强了智能变电站的运维便利性和可靠性。     

基于测试路径集运算的类回归测试策略研究

从基于状态的类测试策略出发,提出了一种基于测试路径集运算的类回归测试策略。该策略将回归测试作为一个连续的过程以测试路径为运算对象。对已修改的类重新生成测试集,通过与原测试集进行简单的集合运算从中选取可用于回归测试的测试用例。研究表明,该策略能充分利用历史测试数据,降低运算复杂度,提高回归测试的效率。     

边界扫描测试的自适应完备诊断算法的优化

IEEE1149.1边界扫描机制是一种新型的VLSI电路测试及可测性设计方法,在边界扫描测试过程中生成合理的测试向量集是有效应用边界扫描机制对电路系统进行测试的关键。在分析传统边界扫描测试生成算法和W步、C步自适应测试生成算法的基础上,提出了一种改近的自适应测试生成算法。实验表明该算法具有完备的诊断能力和紧凑性指标较低的优点,是一种性能优良的完备测试生成算法。     

测试设备的面向用户报表方案设计

一些测试设备的测试数据报表格式固定,与用户的文档规范不相符,不便于用户直接使用。介绍了一种面向用户的测试设备报表方案,测试设备软件用Visual C＋＋开发,通过ActiveX数据对象从数据库中读取存储的测试数据后,利用Microsoft Office Word模板生成Word报表。在测试数据数量确定的情况下,用户通过修改Word模板可定制报表格式,提高了系统开发效率,便于用户使用。     

An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

We present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works where the scan chain is partitioned only based on the excitation properties of the flip-flops (FFs), our work considers both the excitation and propagation properties of the scan FFs. In the proposed scan architecture, the scan chain is partitioned to maximize the overlapping between the excitation and propagation on different fault sets. The scan architecture also allows the entire set of detectable faults in the circuit under test (CUT) to be detected with only a portion of the scan elements active at a time, and thereby completely eliminates the need for the "serial full-scan" mode which is inefficient for both the test time and test power. Experimental results show that by introducing minimal hardware overhead, and without sacrificing fault coverage, an average peak power reduction of 22.8%, average power reduction of 41.6%, and an average reduction of 18.5% on the test application time can be achieved, compared with the ordinary full-scan architecture     

A New Test Point Selection Method for Analog Continuous Parameter Fault

Discrete hard fault is always tested in existing node selection methods for analog circuit diagnosis. Actually, analog component parameter changes continuously and output node voltages distribute in a continuous voltage interval. In this paper, an novel test node selection method is proposed for continuous parameter shifting (CPS) fault. Firstly, CPS faults are sampled by parameter scan simulation in a single test frequency. Collected node voltages are seen as a data set in a statistical distribution. Secondly, ambiguous faults are identified according to the independent distributions of all CPS faults. The independence of CPS fault sample is deduced by Kruskal-Wallis non-parametric testing. Then, new fault dictionaries are generated for each test node according to ambiguous interval. The proposed fault dictionary represents the mutual independence of each pair of CPS faults. Finally, as fault dictionaries are considered as connected graphs, the optimal test nodes are selected based on an improved depth first search (DFS) algorithm. The effectiveness of method is verified by testing linear and nonlinear circuits.     

Test data compression using alternating variable run-length code

This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.     

Test data compression using interval broadcast scan for embedded cores

The paper proposes a new test data compression scheme for testing embedded cores with multiple scan chains. The new compression scheme allows broadcasting identical test data to several scan chains whenever the cells in the same depth are compatible for the current application test pattern. Thus, it efficiently utilizes the compatibility of the scan cells among the scan chain segments, increases test data run in broadcast mode and reduces test data volume and test application time effectively. It does not need complex compressing algorithm and costly hardware. Experimental results demonstrate the efficiency and versatility of the proposed method.     

Diagnostic Test Set Minimization and Full-Response Fault Dictionary

We minimize a given test set without loss of diagnostic resolution in full-response fault dictionary. An integer linear program (ILP), formulated from fault simulation data, provides ultimate reduction of test vectors while preserving fault coverage and pair-wise distinguishability of faults. The complexity of the ILP is made manageable by two innovations. First, we define a generalized independence relation between pairs of faults to reduce the number of fault pairs that need to be distinguished. This significantly reduces the number of ILP constraints. Second, we propose a two-phase ILP approach. In the first phase, using an existing procedure, we select a minimal detection test set. In the second phase, additional tests are selected for the undiagnosed faults using a newly formulated diagnostic ILP. The overall minimized test set may be only slightly longer than a one-step ILP optimization, but has advantages of reducing the minimization problem complexity and the test time required by the minimized tests. Benchmark results show potential for significantly smaller diagnostic test sets.     

Constraint Based Criteria: An Approach for Test Case Selection in the Structural Testing

The selection of test cases to satisfy a structural testing criterion is a very important task because it concerns the quality of the generated test cases. The question is “How to select a test case or path to cover an element required by a structural criterion?” The Constraint Based Criteria are proposed with the goal of answering this question and improving the efficacy, that is, the number of revealed faults. These criteria permit the use of different testing strategies by associating constraints to the required elements. The constraints describe faults generally not revealed by the structural technique. The Constraint Based Criteria can also be used to assess test data sets adequacy.     

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibility.     

Logic Design Validation via Simulation and Automatic Test Pattern Generation

We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.     

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

This paper proposes novel algorithms for computing test patterns for transition faults in combinational circuits and fully scanned sequential circuits. The algorithms are based on the principle that s@ vectors can be effectively used to construct good quality transition test sets. Several algorithms are discussed. Experimental results obtained using the new algorithms show that there is a 20% reduction in test set size, test data volume and test application time compared to a state-of-the-art native transition test ATPG tool, without any reduction in fault coverage. Other benefits of our approach, viz. productivity improvement, constraint handling and design data compression are highlighted.     

"龙腾"S2微处理器测试结构设计

介绍了"龙腾"52微处理器测试结构设计方法,详细讨论了采用全扫描测试、内建自测试(BIST)等可测性设计(DFT)技术.该处理器与PC104全兼容,设计中的所有寄存器采用全扫描结构,设计中的存储器采用内建自测试,整个设计使用JTAG作为测试接口.通过这些可测性设计,使芯片的故障覆盖率达到了100%,能够满足流片后测试需求.