Realization of Tunable Pole-Q Current-Mode OTA-C Universal Filter

A realization of a current-mode operational transconductance amplifier-capacitor (OTA-C) universal filter with tunable pole-Q is proposed. A biquadratic band-reject function is used as the initial synthesis function based on three integrator blocks. Consequently, the proposed filter uses a total of three multiple-output OTAs and three grounded capacitors. Five types of transfer functions, namely, low-pass, high-pass, band-pass, band-reject, and all-pass responses, can be obtained without changing the circuit topology. The pole-Q (Q ₀) and the pole-frequency (ω ₀) parameters are independently tuned. The Q ₀ and ω ₀ parameters are electronically tuned by adjusting the transconductance gains of the OTAs. Furthermore, Q ₀ can be tuned by varying the capacitor manually without affecting ω ₀. SPICE simulation results of the proposed filter are presented.     

New topology for a variable differential delay line using the FGMOS transistor

In this study, we show that floating gate MOS (metal oxide semiconductor) transistors support a low-voltage and low-power variable analogue differential delay line circuit for signals in the audio frequency range. The delay time is dependent and accomplished by a variable bias voltage. Attention is focussed on the fact that the topology will be implemented taking into account low-voltage and low-power. The CMOS (complementary metal oxide semiconductor) circuit design is based on the G _m ? C low-pass linear integrator as the main core. This way, a delay line circuit with two taps was implemented in a 1.2-μm CMOS technology. The experimental results show a spurious free dynamic range of 56 dB, a total harmonic distortion of 0.56% and power dissipation of 52 μW with a supply voltage of 1.5 V.     

Design of High Dynamic Range Fully Integratable Translinear Filters

This paper addresses the non-linear noise and dynamic-range properties of bipolar and MOS (both in weak and in strong inversion) translinear integrators, following a systematic top-down approach. Several design principles to achieve an optimal dynamic range are derived. A qualitative comparison of a bipolar or weak-inversion class-AB translinear integrator and the well-known linear g _m – C integrator reveals that the former is an interesting candidate, especially for low-voltage and/or low-power operation. As an example, a ±1.65-V bipolar translinear integrator is presented that makes dynamic-range optimization possible by adjusting just one bias current. Its application in an audio filter yields a 63-dB dynamic range and a virtual dynamic range of 76 dB, while the current consumption can be as low as 310 nA.     

600V HVIC高噪声抑制电平移位电路

A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block’s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.     

Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (V_t) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (V_h) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the V_t of the proposed circuit increased from 14 V to 27.8 V, and V_h increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V.     

A CMOS transconductance element with improved DC gain and wide bandwidth for VHF applications

The design of a fully-differential, highly linear, voltage-tunable CMOS transconductance element with improved gain performance and wide bandwidth is described. A negative resistance technique for compensation of the parasitic output resistance of the transconductor circuit is employed without requiring extra internal nodes. As a result, dc-gain enhancement is obtained without any bandwidth penalty. SPICE simulations show that for a standard 3m CMOS technology with a power supply of ±5V, for most useful bias conditions THD is much lower than 1% for a 2V _RMS , 5MHz input sine wave; the tuning range of g _m is 36S to 265S. Finally the improved transconductance circuit is presented with an application to a transconductance-capacitor integrator with several tens of megahertz bandwidth.This work was supported in part by the State Scientific Research Committee, Poland, Grant No.8 S501 024 07, and by the National Science Foundation, USA, Grant No. MIP 91-21360.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Lowering supply voltage,V _DD, is the most effective means to reduce power dissipation of CMOS LSI design. In lowV _DD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage,V _th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to lowV _th, while the second approach degrades worst case circuit speed caused byV _th fluctuation in lowV _DD. This paper presents two circuit techniques to solve these problems, in both of whichV _th is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raisesV _th in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reducesV _th fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 VV _DD.     

Digitally programmable CMOS transconductor for very high frequency

This paper describes a new approach for realizing digitally programmable VHF/UHF transconductors compatible with pure digital CMOS technologies. A programmable/tunable transconductor, based on a parallel connection of unit cascode cells, is used to implement a fully balanced current-mode G_m–C integrator to operate over the 30–200 MHz range with more than 70 dB of dynamic range for 1% of THD.     

Large Dynamic Range High Frequency Fully Differential CMOS Transconductance Amplifier

A large dynamic range high frequency fully differential CMOS transconductance amplifier is introduced. It is based on the linear transconductance element proposed in [8] combined with the common-mode feedback circuit in [9]. The original transconductance and common-mode circuits which use two supply voltages are modified for operation under a single power supply. The performance of the complete transconductance amplifier is analysed in details. Simulation results of the whole circuit are also presented, which show that with a single 5 V supply, bandwidth in excess of 300 MHz, THD below 0.7% for a 1 V _pk–pk differential input signal, and dynamic range in excess of 70 dB can be achieved for the fully differential transconductance amplifier.     

Robust Nonlinear H ∞ State Feedback Control of Polynomial Discrete-Time Systems: An Integrator Approach

This paper investigates the problem of designing a nonlinear H _∞ state feedback controller for polynomial discrete-time systems with norm-bounded uncertainties. In general, the problem of designing a controller for polynomial discrete-time systems is difficult, because it is a nonconvex problem. More precisely, in general, its Lyapunov function and control input are not jointly convex. Hence, it cannot be solved by semidefinite programming. In this paper, a novel approach is proposed, where an integrator is incorporated into the controller structure. In doing so, a convex formulation of the controller design problem can be rendered in a less conservative way than the available approaches. Furthermore, we establish the interconnection between robust H _∞ control of polynomial discrete-time systems with norm-bounded uncertainties and H _∞ control of scaled polynomial discrete-time systems. This establishment allows us to convert the robust H _∞ control problems to H _∞ control problems. Then, based on the sum of squares (SOS) approach, sufficient conditions for the existence of a nonlinear H _∞ state feedback controller are given in terms of solvability of polynomial matrix inequalities (PMIs), which can be solved by the recently developed SOS solvers. A tunnel diode circuit is used to demonstrate the validity of this integrator approach.     

一种面向多标准无线收发器的低功耗宽调谐范围基带滤波器设计

本论文提出了一种面向多标准收发器的具有精确片上调谐电路的低功耗宽调谐范围基带滤波器。设计的滤波器是由三级Active-Gm-RC类型的双二次单元级联组成的六阶巴特沃斯低通滤波器。采用改进的线性化技术来提高低通滤波器的线性度。论文提出了一种新的匹配性能与工艺无关的跨导匹配电路和具有频率补偿的频率调谐电路来增加滤波器的频率响应精度。为了验证设计方法的有效性,采用标准的130nm CMOS工艺对滤波器电路进行流片。测试结果表明设计的低通滤波器带宽调谐范围为0.1MHz-25MHz,频率调谐误差小于2.68%。滤波器在1.2V的电源电压下,功耗为0.52mA到5.25mA,同时取得26.3dBm的带内输入三阶交调点。     

A low-noise high-precision analog front end system for biopotential signals recording application

A high precision and low noise analog front end system is proposed in this paper for recording biopotential signals. The system consists of a capacitor-coupled chopper instrument amplifier (CCIA) and a continue-time (CT) Δ? analog to digital converter (ADC). In order to avoid off-chip low-noise reference, a chopper bias circuit is employed to provide low noise bias for CCIA. A positive feedback loop improves the input impedance of CCIA, and a ripple reduction loop based active integrator eliminates the ripple caused by chopping. A new switch-capacitor integrator is employed in the DC servo loop (DSL) to suppress electrode DC offset and save the integrator capacitor area. The CTΔ? modulator employs an energy-efficient 2nd-order structure consisting of a cascade of integrators with feedforward topology, which is unconditionally stable. The CCIA in the proposed analog front end system achieves an input-referred noise of 1.36 μV_rms (0.5?100 Hz), and the CTΔ? ADC achieves a signal noise distortion ratio (SNDR) of 96.2 dB, which are state of the art. The analog front end system is simulated using the standard 0.18 µm CMOS process, and the total power consumption with a 1.8 V supply is less than 112.5 µW.

     

The Effect of Gradual Fluorination on the Properties of FnZnPc Thin Films and FnZnPc/C60 Bilayer Photovoltaic Cells

Motivated by the possibility of modifying energy levels of a molecule without substantially changing its band gap, the impact of gradual fluorination on the optical and structural properties of zinc phthalocyanine (F_nZnPc) thin films and the electronic characteristics of F_nZnPc/C₆₀ (n = 0, 4, 8, 16) bilayer cells is investigated. UV–vis measurements reveal similar Q‐ and B‐band absorption of F_nZnPc thin films with n = 0, 4, 8, whereas for F₁₆ZnPc a different absorption pattern is detected. A correlation between structure and electronic transport is deduced. For F₄ZnPc/C₆₀ cells, the enhanced long range order supports fill factors of 55% and an increase of the short circuit current density by 18%, compared to ZnPc/C₆₀. As a parameter being sensitive to the organic/organic interface energetics, the open circuit voltage is analyzed. An enhancement of this quantity by 27% and 50% is detected for F₄ZnPc‐ and F₈ZnPc‐based devices, respectively, and is attributed to an increase of the quasi‐Fermi level splitting at the donor/acceptor interface. In contrast, for F₁₆ZnPc/C₆₀ a decrease of the open circuit voltage is observed. Complementary photoelectron spectroscopy, external quantum efficiency, and photoluminescence measurements reveal a different working principle, which is ascribed to the particular energy level alignment at the interface of the photoactive materials.     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted (near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain (V_ds) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.     

The impact of PMOST bias-temperature degradation on logic circuit reliability performance

This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product's speed (F_max) and minimum allowed operating voltage (V_ccmin). BT degradation occurs during the product Burn-In and under the normal circuit operation. The interaction of device degradation and circuit performance is explained. Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanism and degradation models are proposed to explain the interaction of fluorine with device and circuit reliability. Process optimization, such as fluorine implant, can be used to reduce the pMOST BT impact on circuit degradation. Reliability guardband in F_max and V_ccmin is recommended, as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime. A guardband methodology is also discussed in the paper.     

Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs

A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. A 22-dB amplifier relaxes the design constraints of the analog front-end (AFE). The integrator non-idealities in the AFE of the sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. The proposed half- (f _s/2) and quarter-rate (f _s/4) LMS calibration schemes reduce computational complexity and achieve more than 2.5× savings in digital power consumption for low-OSR (over-sampling ratio) ΔΣ ADCs, which require higher adaptive filter orders and sampling frequencies. The proposed scheme can have further applications in serial-link I/O and sub-band echo cancellation architectures.     

Dye‐sensitized TiO2 solar cells based on nanocomposite photoanode containing plasma‐modified multi‐walled carbon nanotubes

A series of anatase TiO₂‐based nanocomposite incorporated with plasma‐modified multi‐walled carbon nanotubes (MWNTs) was prepared by physical blending and shows its capability for efficient electron transport when used as photoanode in dye‐sensitized solar cells (DSSCs). These MWNTs characterized with good dispersal performance were obtained by functionalization technique via in situ plasma treatment and subsequent grafting with maleic anhydride (MA) onto the external walls reported previously. Compared with the conventional DSSCs, the TiO₂ film with 1D carbon nanotubes possesses more outstanding ability to transport electrons injected from the excited dye within the device under illumination. As a result, at an optimum addition of 0.3 wt% MWNTs‐MA in TiO₂ matrix, the photocurrent–voltage (J–V) characteristics showed a significant increase in the short‐circuit photocurrent (J_sc) of 50%, leading to an increase in overall solar conversion efficiency by a factor of 1.5. Electrochemical impedance spectroscopy analyses reveal that the MWNTs‐MA/TiO₂ incur smaller resistances at the photoanode in assembled DSSCs when compared with those in the anatase titania DSSCs. These features suggest that the conducting properties of the MWNTs‐MA within the anodes are crucial for achieving a higher transport rate for photo‐induced electrons in TiO₂ layer by exhibiting lower resistance in the porous network and hence retard charge recombination that could result in poor conversion efficiency. Copyright © 2012 John Wiley & Sons, Ltd.