The influence of BF2 and F implants on the 1/f noise inSiGe HBTs with a self-aligned link base

A study is made of 1/f noise in SiGe heterojunction bipolar transistors (HBTs) fabricated using selective growth (SEG) of the Si collector and nonselective growth (NSEG) of the SiGe base and Si emitter cap. The transistors incorporate a self-aligned link base formed by BF ₂ implantation into the field oxide below the p⁺ polysilicon extrinsic base. The influence of this BF₂ implant on the 1/f noise is compared with that of a F implant into the polysilicon emitter. Increased base current noise S_IB and base current are seen in transistors annealed at 975°C, compared with transistors annealed at 950 or 900°C. At a constant collector current, both the BF₂ and F implants reduce S_IB, whereas at a constant base current, only the BF₂ implant reduces S_IB. This result indicates that the BF₂ implant decreases the intensity of the base current noise source whereas the F implant decreases the base current. The proposed explanation for the increased 1/f noise is degradation of the surface oxide by viscous flow at 975°C under the influence of stress introduced during selective Si epitaxy. The influence of the BF₂ implant on the noise is explained by the relief of the stress and hence the prevention of viscous oxide flow     

DPSA双极器件中的1/f噪声特性研究

在现代高性能模拟集成电路设计中,噪声水平是影响电路性能的关键因素之一。研究了双多晶自对准高速互补双极NPN器件中发射极结构对器件直流和低频噪声性能的影响。实验结果表明,多晶硅发射极与单晶硅界面超薄氧化层以及发射极几何结构是影响多晶硅发射极双极器件噪声性能的主要因素。     

Modeling the variation of the low-frequency noise in polysiliconemitter bipolar junction transistors

The variation of the low-frequency noise in polysilicon emitter bipolar junction transistors (BJTs) was investigated as a function of emitter area (A_E). For individual BJTs with submicron-sized A _E, the low-frequency noise strongly deviated from a 1/f-dependence. The averaged noise varied as 1/f, with a magnitude proportional to A_E^-1, while the variation in the noise level was found to vary as A_E^-1.5. A new expression that takes into account this deviation is proposed for SPICE modeling of the low-frequency noise. The traps responsible for the noise were located at the thin SiO₂ interface between the polysilicon and monosilicon emitter. The traps' energy level, areal concentration and capture cross-section were estimated to 0.31 eV, 6×10⁸ cm^-2 and 2×10^-19 cm ², respectively     

Low-frequency noise sources in polysilicon emitter BJT's: influenceof hot-electron-induced degradation and post-stress recovery

The noise properties of polysilicon emitter bipolar transistors are studied. The influences of the various chemical treatments and annealing temperatures, prior and after polysilicon deposition, on the noise magnitude are shown. The impact of hot-electron-induced degradation and post-stress recovery on the base and collector current fluctuations are also investigated in order to determine the main noise sources of these devices and to gain insight into the physical mechanisms involved in these processes     

Effect of interfacial oxide thickness on 1/f noise in polysilicon emitter BJTs

The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (R/sub S/) were used to investigate the relative contribution of each individual noise source from the base current (S/sub IB/), the collector current (S/sub IC/) and, the internal emitter and base series resistances (S/sub Vr/). When the voltage noise power spectral densities S/sub VC/ and S/sub VB/ were measured across resistances in series with the collector and base, respectively, using a relatively large R/sub S/ (/spl sim/1 M/spl Omega/), S/sub IB/ was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities S/sub VC/ and S/sub VE/ were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low R/sub S/ value, S/sub Vr/ was found to have the dominant noise contribution at higher bias currents. IFO was found to increase S/sub IB/, S/sub IC/, and S/sub Vr/. S/sub IB/ was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas S/sub IC/ was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. S/sub Vr/ was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO.     

The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated     

Measurement and control of a residual oxide layer on TiSi2 films employed in ohmic contact structures

An inadvertent oxide layer is formed on a titanium disilicide (TiSi₂) film following various wet and dry processes in a manufacturing environment. The use of H₂SO₄:H₂O₂:H₂O (1:1:5) as a wet etch for excess Ti metal, prior to the high temperature anneal used to form a subsequent TiSi₂ layer, is identified as the source of the undesired oxide via multiwavelength spectroscopic ellipsometry and Auger electron spectrometry studies. This inadvertent oxide layer on TiSi₂ is shown to form bad electrical contacts and is a contributing source to large standby currents in polysilicon gate shunts. Spectroscopic ellipsometry is shown herein as a unique analytical tool to determine both the thickness and structure of this poorly structured oxide during process development. A single wavelength ellipsometer monitoring scheme for both the appearance as well as the thickness of this inadvertent oxide layer is proposed for use in high-volume manufacturing     

Polysilicon emitter p-n-p transistors

In-situ boron-doped polysilicon has been used to form the emitter in p-n-p transistors. Various polysilicon deposition conditions, interface preparation treatments prior to deposition, and post-deposition anneals were investigated. Unannealed devices lacking a deliberately grown interfacial oxide gave effective emitter Gummel numbers G_E of 7-9×10^-12s cm^-4 combined with emitter resistances R_E of approximately 8 μΩcm². Introduction of a chemically grown interfacial oxide increased G_E to 2×10 ¹⁴s cm^-4, but also raised R_E by a factor of three. Annealing at 900°C following polysilicon deposition raised G_E values for transistors lacking deliberate interfacial oxide to approximately 6×10¹³s cm^-4, but had little effect of G_E for devices with interfacial oxide. Both types of annealed devices gave R_E values in the range 1-2 μΩcm²     

A new model for the low-frequency noise and the noise levelvariation in polysilicon emitter BJTs

Presents a new, physically-based model for the low-frequency noise in high-speed polysilicon emitter bipolar junction transistors (BJTs). Evidence of the low-frequency noise originating mainly from a superposition of generation-recombination (g-r) centers is presented. Measurements of the equivalent input noise spectral density (SIB) showed that for BJTs with large emitter areas (AE) S(I_B) is proportional to 1/f, as expected. In contrast, the noise spectrum for BJTs with submicron A_E showed a strong variation from a 1/f-dependence, due to the presence of several g-r centers. However, the average spectrum 〈S(I_B)〉 has a frequency dependence proportional to 1/f for BJTs with large as well as small A_E. The proposed model, based only on superposition of g-r centers, can predict the frequency-, current-, area-, and variation-dependency of 〈S(I_B)〉 with excellent agreement to the measured results     

RTS noise in submicron SiGe epitaxial base bipolar transistors

In this paper, we report a comprehensive study of Random Telegraph Signal (RTS) noise in SiGe epitaxial base bipolar transistors. We analyse the multilevel fluctuations of base and emitter forward currents before and after reverse stress on the emitter-base junction. We show the influence of the chemical treatment preceeding polysilicon emitter deposition on noise properties. We identified that RTS noise arises from different regions in the device : the silicon/polysilicon interface if an oxidizing surface preparation is used, and the emitter periphery after stress-induced degradation. Temperature and bias dependent measurements allowed us to characterize these defects (activation energy, defect type), to analyse their impact to the low frequency noise properties of these transistors and to discuss the role of hot carrier stressing.     

Low-frequency noise spectroscopy of polycrystalline siliconthin-film transistors

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap     

Improvement of RCA transistor using RTA annealing after theformation of interfacial oxide

A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 × 8 μm². The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively     

1/f noise characterization of base current and emitter interfacialoxide breakup in n-p-n polyemitter bipolar transistors

We propose using base 1/f noise to characterize the distribution of diffusion and tunneling components of base-current (I_b) at the emitter poly/monosilicon interface in n-p-n polyemitter transistors. A noise model is constructed to interpret the I_b 1/f noise (S _iEB) dependence on these combined currents. Measured I_b dependences of S_iEB increase progressively from I_b^1.2 to I_b^2.0 for transistors having emitter structures concomitant with increasing current gains and series emitter resistances ranging between 115-1800 and 7-33Ω, respectively. This is indicative of tunneling components in I_b^2.0 that increase with higher interfacial oxide continuity, and persist in epitaxially realigned emitters     

Process investigations for a 30-GHz fT submicrometerdouble poly-Si bipolar technology

Major process issues are investigated to establish a manufacturable process for a 30-GHz f_T deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000°C in order to maintain an acceptable integrity of TiSi₂ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975°C and 1000°C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process     

Quantitative correlations between the performance of polysiliconemitter transistors and the evolution of polysilicon/silicon interfacialoxides upon annealing

Correlations between oxide breakup and polysilicon-emitter bipolar characteristics are quantitatively established by introducing kinetic terms for oxide breakup in the bipolar transport equations. It is verified that emitter resistance largely depends on the continuity of the interfacial oxide. Similarly, oxide breakup is seen to directly result in an increase in base current up to temperatures of ~950°C (for 30-min anneals), above which the changing structure of the polysilicon is found to play the dominant role in the rise of base current. These observations establish that both the interfacial oxide and the polysilicon layer are responsible for the enhanced gain seen in polysilicon emitter transistors. With the contributions of the oxide and the polysilicon quantitatively understood, it becomes possible to simulate polysilicon emitter device characteristics as a function of process conditions     

Impact of the interfacial layer on the low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks

The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n- and p-channel MOSFETs with high-/spl kappa/ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices. 2) A significant increase of the Hooge's parameter is observed for both types of MOSFETs. These experimental findings indicate that bringing the high-/spl kappa/ layer closer to the Si-SiO/sub 2/ interface enhances the 1/f noise mainly due to mobility fluctuations.     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

Effective recombination velocity of polysilicon contacts for bipolar transistors

The effective surface recombination velocity is determined analytically for a doped polysilicon contact to the emitter of a bipolar transistor in the presence of a thin interfacial oxide layer. Results are presented for various doping levels, oxide thicknesses and barrier heights. The analysis considers both tunnelling and thermionic emission through the interface.     

Analysis of emitter efficiency enhancement induced by residualstress for in situ phosphorus-doped polysilicon emitter transistors

This paper analyzes the enhancement of emitter efficiency in in situ phosphorus-doped polysilicon (IDP) emitter transistors, whose polysilicon emitter is crystallized from an in situ phosphorus-doped amorphous Si film. There are two factors that enhance the emitter efficiency of the IDP emitter. One is a potential barrier at the LDP/substrate interface produced by residual stress in the IDP layer. The other is a very thin oxide layer at the interface, which prevents epitaxial growth at the interface. We have distinguished between the emitter efficiency enhancement due to each of these two factors by analyzing the characteristics of three types of IDP emitter in which the residual stress and the thin oxide layer at the interface are controlled differently. We found that the potential barrier due to the residual stress increases the emitter efficiency from about two times to about eight times depending on the emitter size, and that the thin oxide layer at the interface increases the emitter efficiency by about three times     

Trade-off between emitter resistance and current gain inpolysilicon emitter bipolar transistors with intentionally growninterfacial oxide layers

Experimental measurements of emitter resistance and current gain in polysilicon emitter bipolar transistors that have received annealing to break up an intentionally grown RCA oxide interfacial layer are presented. An anneal of 900°C for 10 min in a nitrogen ambient of the interfacial layer prior to polysilicon doping resulted in a decrease in emitter resistance by approximately a factor of 5, with an increase in base saturation current of only 25% while still maintaining a current gain of around 500. The authors believe that this is the largest trade-off in emitter resistance versus current gain demonstrated so far for polysilicon transistors with an RCA interfacial layer. These results support a theory previously proposed by the authors (1991) predicting that significant trade-offs between emitter resistance and current gain can be obtained if an intentionally grown interfacial oxide layer in polysilicon emitter bipolar transistors is annealed so as to induce only partial breakup such that most of the layer remains intact