数字电视图像清晰度

导出了以电视线表示的数字电视图像清晰度计算方法及其理论值，指出基于电子束扫描的CRT电视显像管与LCD，PDP，DLP，LCoS和OLED等固有分辨力显示器（屏）所显示图像的清晰度之间有很大不同，而测定电视图像清晰度不仅要合理设计和精确生成清晰度测试图，而且必须在规范的测试条件下采用正确的方法，并对测试数据进行处理。     

像素比例校正及其在生成清晰度测试图中的应用

针对按计算机方像素生成的图案显示在非方像素显示系统时出现几何失真，提出了基于像素宽高比(PAR)的比例校正算法，并用于建立屏幕虚拟几何中心、计算参数K和导出水平或垂直最高空间分辨率与参数ρ0的关系，从而优化了电视图像清晰度测试图生成算法。实验表明，据此能精确生成多种标准、不同格式的电视测试信号、图、卡和运动序列。     

超高清晰度电视复合测试图设计与生成

给出了设计、生成的UHDTV4K复合测试图,阐述了其应用;导出了测试图同心度、重显率和清晰度等测试信号单元的数学模型,并逐像素计算生成;设计了固有分辨力显示屏分辨力观测信号;引入了色域和色度视角主观评价信号;集成了彩条和灰阶等多种观测信号.     

数字图像清晰度

给出了数字图像清晰度的多种表达方式,指出空间分解力反映了数字图像清晰度的实质,应推荐使用;定量分析不同数字图像系统在各个方向上所能达到的图像清晰度理论值的计算方法和实际值的估算方法;为适应我国数字视频技术和产业的蓬勃发展,指出并实验了用数字处理技术,在不增加传输、记录开销条件下,提高重建图像清晰度的途径;设计并用计算机生成了多种数字电视清晰度测试信号和图卡。     

标准清晰度数字电视主观评价用测试图像

本文简要介绍新发布的广播电视行业标准<标准清晰度数字电视主观评价用测试图像>的主要内容、制作测试图像的基本准则和测试图像在实际应用中的情况.     

用中央电视台新测试图目测大屏幕彩电图像效果

一、水平清晰度的目测大屏幕彩电水平清晰度的实际值与有些生产厂广告中发布值相差很大。一般广告中均声称为500线以上,甚至达800线。实际情况如何呢?利用中央电视台5～8套节目的新测试图,就可以作出清晰度大概为多少线的判断。新测试图右侧1/3处设有7条楔形排列的弧形线条,并注明相应的频率3、4、5MHz。其含意为:当屏幕上的楔形线条较清晰、并可以看清每条线都有明     

彩电图象清晰度增强电路AN5342K

图象清晰度是电视机最主要的技术参数，为了提高图象清晰度，电子技术工作者花费了大量的精力，做了大量的工作。日本松下公司生产的ＡＮ５３４２Ｋ图象清晰度增强电路是较为成功的一种，它已普遍用于高档大屏幕彩色电视机中。ＡＮ５３４２Ｋ的内部电路（图１）主要包括图...     

最新影音产品简介

目前影音新品不断涌现．其中有不少的技术含量极高。设计理念独特新奇的精品．如三星公司的102英寸特大屏幕等离子显示屏；东芝和佳能联合研制的SED新型电视机．这种SED平板电视机生成的图像有惊人的细腻度，出奇的清晰度和亮度，有如同CRT电视机那样的暗部细节，机身纤薄、美观（图1），东芝打算在2006年初推出60英寸、1080p的正式SED电视机产品；     

用气导和骨导语言传输验证“汉语清晰度诊断押韵测试(DRTC)法”

我们依据电子部第三十所编制的“汉语清晰度诊断押韵测试(DRTC)法”对气导和骨导语言传输进行汉语清晰度测试。本文给出3这次测试的结果,分析了影响被测语言传输系统清晰度的原因,证明用“DRTC”法测试除给出系统的汉语清晰度得分外,还能依据特征分类的清晰度值对被测系统性能进行诊断分析。     

VCD视盘机视频特性测试技术的研究

基于对ＶＣＤ视盘机视频信号处理过程的分析，研究了对其进行视频测试的原理和方法；用计算机生成了符合ＩＥＣ标准和是中部标的ＶＣＤ测试信号；重新设计、生成了一系列新的测试信号和图、卡。它们具有准确、灵活、便于应用等特点。     

Efficient Path Delay Testing Using Scan Justification

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip‐flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS’89 benchmark circuits show that the number of testable paths can be increased by about 45% over the conventional functional justification.     

有源多波束天线方向图测试方法研究

论述了利用高精度三轴天线测试转台,测试有源多波束天线立体方向图的方法。简述了天线立体方向图的测量程序。给出了用二维坐标表示多波束立体方向图的方法,并简述了利用MATLAB软件对测试数据进行处理获得多波束天线立体方向图的方法,对方向图测试误差进行了分析。最后,给出了某工程有源多波束天线方向图的测试结果。实践证明:该方法是切实可行的。     

BISTing Datapaths under Heterogeneous Test Schemes

In this paper, we present a fast and efficient algorithm for BISTing datapaths described at the Register Transfer (RT) level. This algorithm is parameterized by user defined tuning factors allowing tradeoffs between fault coverage, area overhead and test application time. This algorithm is generic in the sense it handle and mixes heterogeneous test pattern generators and compactors.     

Mixed-Mode BIST Using Embedded Processors

In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not completely random pattern testable, the test programs have to generate deterministic patterns after random testing. Usually the random test part of the program requires long run times whereas the part for deterministic testing has high memory requirements.In this paper it is shown that an appropriate selection of the random pattern test method can significantly reduce the memory requirements of the deterministic part. A new, highly efficient scheme for software-based random pattern testing is proposed, and it is shown how to extend the scheme for deterministic test pattern generation. The entire test scheme may also be used for implementing a scan based BIST in hardware.     

Sequential recognition using a nonparametric ranking procedure

In the problems of statistical pattern recognition, it has become increasingly known that there are many applications in which parametric assumptions regarding the pattern statistics are not justified. This paper treats a nonparametric design of a sequential recognition machine which uses the optimum property of Wald's sequential probability ratio test (SPRT). For the case of binary classification, a sequential ranking procedure is found useful in a two-sample problem in which we wish to test the hypothesis against the Lehmann alternatives, based on the successively ranked observations. The test procedure is then analyzed in terms of the performance criterion which in this case is the expected number of observations, with specified error probabilities. A generalization procedure of multiple classification is also given as a direct extension. Computer-simulated experiments have illustrated the effectiveness of this test procedure in the recognition of handwritten English characters, where the nonparametric method seems to be necessary and appropriate.     

考虑串扰影响的时延测试

超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。本文介绍了一个基于波形敏化的串扰时延故障测试生成算法。该算法以临界通路上的串扰时延故障为目标故障进行测试产生．大大提高了算法的效率。实验表明，以该算法实现的系统可以在一个可接受的时间内。对一定规模的电路的串扰时延故障进行测试产生。     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

时域开槽天线阵辐射特性的实验研究

将时域天线组成阵列是改善超宽带雷达系统技术性能一条行之有效的途径,因而对时域天线阵辐射或接收的波形变换和畸变规律进行研究,是十分必要的;利用时域天线的时域波形、归一化能量方向图、归一化峰值方向图来分析开槽天线阵的测试结果,得出关于时域天线阵接收特性有价值的结论。     

Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits

By their nature, mixed-signal circuits have to be tested for both structural integrity and parametric performance. For the example of data converters we review test pattern selection strategies geared towards structural and performance testing. We introduce a novel test pattern selection strategy that merges both objectives, and by that we achieve a significant reduction in the size of the set of test patterns applied on the production line.     

An Effective Test and Diagnosis Algorithm for Dual‐Port Memories

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual‐port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual‐port memories.