双栅掺杂隔离肖特基MOSFET的解析模型

通过考虑肖特基势垒降低效应求解三段连续的二维泊松方程,建立了双栅掺杂隔离肖特基MOSFET亚阈值区全沟道连续的电势模型。在该电势模型的基础上,推导了阈值电压模型和漏致势垒降低效应的表达式;研究了掺杂隔离区域不同掺杂浓度下的沟道电势分布,分析了沟道长度和厚度对短沟道效应的影响。结果表明,掺杂隔离区域能改善肖特基MOSFET的电学特性;对于短沟道双栅掺杂隔离肖特基MOSFET,适当减小沟道宽度能有效抑制短沟道效应。     

双栅和环栅MOSFET中短沟效应引起的阈值电压下降

基于电荷分享原理 ,推导了双栅和环栅 MOSFET短沟效应引起的阈值电压下降 ,分析了衬底掺杂浓度、栅氧化层厚度及硅膜厚度等因素对阈值电压下降的影响 ,并用数值模拟验证了理论结果 .这些研究结果对进一步开展纳米 CMOS新器件的研究有很好的参考价值和实际意义     

An Analytical Threshold Voltage Model for Fully Depleted SOI MOSFETs

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

双栅和环栅MOSFET中短沟效应引起的阈值电压下降

基于电荷分享原理,推导了双栅和环栅MOSFET短沟效应引起的阈值电压下降,分析了衬底掺杂浓度、栅氧化层厚度及硅膜厚度等因素对阈值电压下降的影响,并用数值模拟验证了理论结果.这些研究结果对进一步开展纳米CMOS新器件的研究有很好的参考价值和实际意义.     

GeSiMOSFET的纵向结构对器件性能的影响

为了研究器件参数对GeSi MOSFET器件性能的影响,本文在建立一个简单的GeSi MOSFET的器件模型的基础上,对GeSi MOSFET的纵向结构进行了系统的理论分析.确定了纵向结构的CAP层厚度、沟道层载流子面密度、DELTA掺杂浓度以及量子阱阱深之间的关系,得出了阈值电压与DELTA掺杂浓度、栅氧化层厚度及CAP层厚度之间的关系,还得出了栅压与沟道载流子面密度、栅氧化层厚度及CAP层厚度之间的关系.并且在此基础上得出了一些有意义的结果.为了更细致、精确地进行分析,我们分别对GeSi PMOSFET和GeSi NMOSFET在MEDICI上做了模拟.     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

薄膜SOI MOS器件阈值电压的解析模型分析

研究了薄膜全耗尽增强型 SOIMOS器件阈值电压的解析模型 ,并采用计算机模拟 ,得出了硅膜掺杂浓度和厚度、正栅和背栅二氧化硅层厚度及温度对阈值电压影响的三维分布曲线 ,所得到的模拟结果和理论研究结果相吻合。     

高k栅介质MOSFETs的二维阈值电压模型

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

2D Threshold-Voltage Model for High-k Gate-Dielectric MOSFETs

给出包括栅电介质与耗尽层区域的边界条件和二维沟道电势分布.根据这个电势分布,得出高k栅介质MOSFET的阈值电压模型,模型中考虑短沟道效应和高k栅介质的边缘场效应.模型模拟结果和实验结果能够很好地符合.通过和一个准二维模型的结果相比较,表明该模型更准确.另外,还详细讨论了影响高k栅电介质MOSFET阈值电压的一些因素.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

Modeling of threshold voltage of a quadruple gate transistor

In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. For numerical simulation, self-consistent Schrodinger-Poisson equations, calibrated by 2D non equilibrium green function simulation, are used. This analytical model not only provides useful physics insight of effects of gate length and body width on the threshold voltage, but also serves as a basis for compact modeling of quadruple gate MOSFETs.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

GaN基HEMT器件结构设计及其性能仿真北大核心

利用Silvaco TCAD器件模拟软件研究了AlGaN/GaN高电子迁移率晶体管(HEMT)器件势垒层的厚度、沟道宽长比和掺杂浓度对器件的转移特性和跨导曲线的影响。结果表明,器件势垒层厚度的变化可以调节器件的电流开关比和开启电压,实现由耗尽型器件向增强型器件的转变;沟道宽长比的改变可以调节器件的开启电压,并且随着沟道宽长比的增加,栅极电压控制量子阱中二维电子气的能力增强;势垒层适量掺杂提高了输出电流,并且使跨导的峰值增大,但过度掺杂会造成器件不易关断情况出现。     

Short channel MOSFET model using a universal channel depletionwidth parameter

We verified a critical rendition that short channel effects depend on junction depth, and showed that junction depth by itself is not important for improving short channel immunity. The depletion region width of a short channel device changes significantly depending on the location along the channel. We proposed a universal channel depletion width parameter that effectively expresses this dependence. Using this parameter, we solved a two-dimensional (2-D) potential distribution and derived a threshold voltage model. The model reproduces the numerical data of sub-0.1-μm gate length devices, including channel doping concentration, gate oxide thickness, drain voltage, and back bias dependencies     

Investigation of high-performance sub-50 nm junctionless nanowire transistors

The performances of the junctionless nanowire transistor (JNT) are evaluated under high-performance (HP) ITRS device technical requirements for the 25 nm technology node. The electrical characteristics of the devices are obtained from numerical simulations. The threshold voltage of JNT can be easily adjusted by changing different variable parameters such as fin width, fin thickness, doping concentration, gate oxide thickness and gate work function. The variation of threshold voltage with physical parameters is analyzed. The current drive is controlled by doping concentration and nanowire size. For gate length down to 25 nm, a 30-40% increase in drain current is also reported by using a fin aspect ratio of 2 instead of 1. Additional source and drain implantation can be applied to improve the current drive.     

Threshold voltage shift in 0.1 μm self-aligned-gate GaAs MESFETs under bias stress and related degradation of ultra-high-speed digital ICs

Bias-temperature stress examinations of self-aligned 0.1 μm length gate GaAs MESFETs have revealed a shift of threshold voltage related to Si doping concentration near the gate sides next to the channel region. With lower doping concentration, the increase in threshold voltage in FETs was faster and a 100 mV increase leads to a 20% reduction of operation speed in digital ICs after forward-biased storage at 200°C. The recovery of the performance under reverse-biased stresses was observed. The degradation is released by increasing Si doping concentration and thus we obtained the prediction of a median life exceeding 10⁶ h at 100°C by setting the Si dose of 4 × 10¹³ cm⁻², which is as high as it can be set without causing serious reduction of breakdown voltage.     

Threshold and punchthrough behavior of laterally nonuniformally doped short-channel MOSFET's

Predictions of gate threshold voltage and punchthrough voltage have been made for short-channel VDMOS and UMOS field-effect transistors using exact, two-dimensional numerical analysis. In these devices the doping concentration varies laterally from source to drain. The threshold voltage is found to be related to the maximum value of channel doping. This correspondence becomes poorer as the channel length is diminished since punchthrough current begins to influence the threshold voltage for short-channel devices. Surface punch-through is predicted for the VDMOSFET whereas bulk punchthrough is found in the UMOS device. A correspondence between the results of two-dimensional computer simulation of punchthrough and the estimations of one-dimensional simplified theory is found.     

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical valueW_{min}which is about 1 µm for 200-A gate oxide 7000-A field oxide and2 times 10^{16}cm^-3substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.     

A modified model for Si/SiGe MOS-gate delta-doped HEMTs

An analytical model for threshold voltage (V_th) and minimum gate voltage (V_tl) of Si/SiGe MOS-gate delta-doped HEMT is presented in this letter. The model is valid for any width of the delta-doped layer and any distance of the layer from the Si/SiO₂ interface. Using the model, V_th and V_tl of a Si/SiGe MOS-gate delta-doped HEMT of known dimensions are calculated. To investigate the effect of variation of the width of the delta-doped layer, the threshold voltage and the minimum gate voltage have been plotted against the width. Medici™ simulation have been performed on the same device to evaluate V_th and V_tl for different delta-doped layer widths. The simulation results are in good agreement with the results found using the analytical model.