一种基于JTAG的SoC片上调试系统的设计

基于SoC的硬件设计,提出了一种基于JTAG的SoC3片上调试系统的设计方法.该调试系统可设置多种工作模式,含有CPU核扫描链和片上总线扫描链.能硬件实现调试启动与停止、断点设置、单步执行及存储访问等调试功能.对外围IP模块调试诊断时,可绕开CPU核,通过片上总线扫描链直接进行读写访问.该调试系统对其他SoC的设计具有一定的参考价值.     

基于RISC-V调试协议的片上调试系统设计与实现

为满足RISC-V架构生态中对RISC-V平台软件调试的需求,设计并实现了一种基于RISC-V调试协议的片上调试系统.该系统通过调试传输模块实现并隐藏调试模块内部寄存器访问逻辑,将其简化为JTAG串行信号实现与宿主机的交互,并通过调试模块实现了调试所必需的处理器全面监控与存储访问功能.在基本调试功能的基础上,进一步实现了总线直接访问、程序缓存和基于触发模块的触发功能,并在兼容RISC-V调试协议的情况下实现了事件序列触发功能.该片上调试系统依托于自研RISC-V处理器硬件平台,通过GDB与OpenOCD构成的宿主机软件环境进行功能测试.经过与其他RISC-V架构处理器对比和FPGA测试表明,该片上调试系统功能丰富,能够满足目前RISC-V平台调试的功能需求.     

一种双核SoC调试系统的设计与验证

调试系统的设计和验证是多核SoC设计中的重要环节。基于某双核SoC的设计,提出一个片上硬件调试构架,利用FPGA构建该调试系统的硬件验证平台。双核SoC调试系统验证平台利用System Verilog DPI,将RealView调试器、Keil C51及目标芯片的验证testbench集成在一起,实现了双核SoC调试系统的RTL级调试验证。利用该平台,在RTL仿真验证阶段可方便地对ARM和8051核构成的双核SoC进行调试,解决仿真中出现的问题,从而有效缩短设计周期,并提高验证效率。该双核SoC调试系统验证平台的实现对其他系统芯片设计具有一定的参考价值。     

风河公司首次推出支持Intel IOP342处理器的多内核片上调试技术

风河公司日前推出了全新的、支持Intel IOP342处理器的多内核片上调试解决方案——Wind RiVer Workbench片上调试工具。该工具运用了一种高性能的JTAG解决方案，不但能够完成硬件调试，还可以实现一个或多个跨多内核运行的、不同操作系统之间的复杂交互调试。从而极大地缩短了用户的。调试一编译一编码”周期。风河公司还将进一步完善多内核片上调试工具，使客户能够更充分地利用Intel IOP342处理器下各种设备软件应用的强大功能，更快地完成新硬件产品的开发。     

支持IOP342处理器的多内核片上调试方案

多内核片上调试解决方案WindRiverWorkbench片上调试工具支持Intel IOP342处理器，不但能够完成硬件调试，还可以实现一个或多个跨多内核运行的不同操作系统之间的复杂交互调试，从而极大地缩短用户的“调试-编译-编码”周期。     

一种基于EJTAG快速在线烧写Flash的设计

介绍了MIPS的KITAG片上调试体系结构、调试流程，分析了当前在线烧写Flash的各种方法。并提出了一种新型的利用片上调试系统快速在线烧写Flash的设计。实验结果表明，该方案比现有方法的效率提高了88％。该方法已经成功运用在基于MIPSCPU的聚芯SoC的FPGA和ASIC版本中。     

基于JTAG的SoC片上调试系统设计

文章提出了一种基于JTAG的SoC片上调试系统设计方法,该系统主要包括JTAG接口和片上调试模式控制单元。通过执行不同的操作指令,该片上调试系统可实现断点设置、单步执行、寄存器和存储器内容监控、在线编程以及程序运行现场设置等调试功能。文章同时说明了片上调试系统的工作原理和硬件架构。     

可重用片上仿真调试协议结构

提出了一种可重用片上仿真调试协议结构,基于此结构设计实现的片上仿真调试逻辑,简单高效,便于重用于新的芯片和新的体系结构.     

基于IEEE 1149.1标准的可重定向片上调试方法

介绍了一种基于IEEE1149．1标准的可重定向的调试方法，详细地分析了一种嵌入式调试模块的内部结构、工作原理、实现过程以及它给处理器核带来的代价，该模块在RTL级只需较少的修改即可集成在多种微处理器核上．完成片上调试的功能。     

CPU中可伸缩低开销的硬件调试器设计

介绍了一种基于JTAG的片上调试的低开销、可伸缩、支持“非侵入性”调试的硬件实现方法。该实现方法是通过在片上调试模块中引入一组映像寄存器，用于跟踪和设置CPU的状态。使用该方法避免了在CPU的关键路径上插入扫描链而限制了CPU性能提高的缺点。此外，本文还阐述了精确硬件断点的实现方法，调试模块实时监视数据地址总线和指令地址总线，当地址与预设值吻合时使CPU进入调试模式，该实现方法支持在程序全速运行时在断点处进入调试模式。本文所提出的方法已经在CK520嵌入式CPU中得到应用和证明。     

基于OCP通信事务的SOC调试控制器

基于OCP通信事务进行SOC调试,提高了调试的抽象级别,对于以通信为核心的多核SOC,可以大大提高调试效率.为实现事务级调试,提出基于OCP通信事务的可配置调试控制器.通过分析OCP通信事务,该控制器根据预先配置的触发条件产生本地和远端调试控制信息,从而控制调试过程.通过对实验设计的仿真和综合,验证了调试控制器的功能,并分析了设计的面积开销.     

On‐Chip Debug Architecture for Multicore Processor

Because of the intrinsic lack of internal‐system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on‐chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run‐stop‐type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG‐based scanning operation. We apply this on‐chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.     

Debug Facilities in the TriMedia CPU64 Architecture

This paper describes debug facilities in the Philips TriMedia CPU64, which is an embedded processor core for multimedia applications. Its architecture provides a VLIW pipeline, support for 64-bit vector data, and virtual memory management. The debug hardware in the TriMedia CPU64 supports two complementary debug strategies. One strategy provides a snapshot of the processor state at certain moments in time, which is achieved by single-step execution and various breakpoint types. The other debug strategy provides continuous monitoring of the processor state by using a PC trace buffer. Precise exceptions are used to provide accurate context switching from application software to debugger software.     

Easily Adaptable On‐Chip Debug Architecture for Multicore Processors

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time‐consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on‐chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run‐stop mode debugging. Compared with the debug architecture that supports the run‐stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on‐chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.     

基于JTAG的SoC芯片调试系统设计

文章提出了一种基于IEEE 1149.1 JTAG协议的SoC调试接口,该设计支持寄存器查看和设置、CPU调试、IP核调试、边界扫描测试等功能。对该接口的整体结构框图到设计都进行了详细的阐述。该接口成功地应用于测控SoC中,具有很好的参考价值。     

Linux系统上复杂系统调试信息重定向的实现

针对目前Linux上复杂应用系统远程调试追踪困难的问题,提出了一种在Linux内核Syslog的基础上再次开发实现的可靠的调试信息重定向方法。该方法支持细化到进程级别的管理,动态的优先级设置,实时的重定向传输,以及不影响系统性能的良好的表现。同时在Ubuntu 12.04和Intel i7平台架构上对该方法的正确性进行了检测验证。     

基于多DSP系统的交叉调试系统的设计和实现

本文介绍了一种由多个DSP构建的并行处理系统,探讨了多DSP系统中实现交叉调试的方法,详细讨论了调试器和目标机调试的具体内容,给出了调试模式下的程序下载方式。实际应用显示,该交叉调试系统能够有效满足多DSP系统的调试需求,拥有较好的多处理器支持性能和较高的性价比。     

Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips

To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The states of the flip-flops and the memory elements are observed and compared with the simulation results. If the chip contains multiple clock domains then these clock domains must be stopped simultaneously, otherwise some of the elements in one or more of the clock domains will capture old data/invalid data. The phenomenon of capturing invalid data is known as data invalidation. This paper describes the data invalidation problem in depth and presents a data invalidation detector circuit. An automated data invalidation analysis tool named DIAna is also presented. By means of experimental results for an industrial SOC, we show the amount of data invalidation that can occur during silicon debug.