一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。     

一种新型低压COMS四象限模拟乘法器

提出了一种采用有源衰减器和全差分电流传输器(FDCCⅡ)为核心的新型低压CMOS四象限模拟乘法器.PSPICE仿真表明,当电源电压为±1.5 V时,电路功耗小于75μW.该乘法器电路具有较好的线性输入范围,达到±1 V,当输入电压范围限于±0.8V时,非线性误差小于0.6%,-3 dB带宽约为10 MHz.     

一种高稳定低功耗CMOS过热保护电路的设计

采用1．2μm CMOS工艺,设计了一种过热保护电路,并利用Cadence Spectre仿真工具对电路进行了仿真,结果表明,电路的输出信号对电源的抑制能力很强,在3．5V以上的电源电压工作下,输出过热保护信号所产生的过热温度点基本保持不变,约为132℃;同时在3V电源电压工作下,电路功耗约为1．05mW,而在9V的高压下工作,功耗仅为14．4mW。由此可见,此电路性能较好,可广泛应用在各种集成电路内部。     

一种宽输入范围的Gillbert模拟乘法器设计

本文分析了基于CMOS工艺设计的Gillbert单元乘法器,改进了原有电路工作电压高的缺陷,使它能在更低的电源电压下工作,并在乘法器的输入级加入有源衰减电路,增大乘法器的输入范围。本文采用上华0.6μmCMOS工艺进行设计,并用Cadence Spectre仿真器对电路进行了仿真,得到3V电源电压下,输入范围为0～2V的模拟乘法器。     

一种低功耗的13位100MS／s采样保持电路

采用TSMC0．18μm 1P6MCMOS工艺设计了一种高性能低功耗采样保持电路。该电路采用全差分折叠增益自举运算放大器和栅压自举开关实现。在3．3V电源电压下,该电路静态功耗仅为16．6mw。在100MHz采样频率时,输入信号在奈奎斯特频率下该电路能达到91dB的SFDR,其有效精度可以达到13位。     

10 Gb/ s 0. 18 􀀁m CMOS 激光二极管驱动器芯片

基于0．18μm CMOS工艺设计的10Gb／s激光二极管驱动器电路。核心单元为两级直接耦合的差分放大器，电路中采用了并联峰化技术和放大级直接耦合技术以扩展带宽，降低功耗。模拟结果表明，在1．8V电源电压作用下该电路可工作在10Gb／s速率上，输入单端峰峰值为0．3V的差分信号时，在单端50Ω负载上的输出电压摆幅可达到1．4V，电路功耗约为85mW。     

一种宽输入范围CMOS模拟乘法器的优化设计

设计了一种基于CMOS工艺设计的宽输入范围的Gilbert单元乘法器.通过在乘法器的输入端加入有源衰减器和电位平移电路,增大了乘法器的输入范围(±4 V).该乘法器采用TSMC 0.35 μm的CMOS工艺进行设计,并用HSpice仿真器对电路进行了仿真,得到了电源电压为±4 V,以及线性电压输入范围为±4 V时,非线性误差小于1.0%,乘法运算误差小于0.3%,x输入端的-3 dB带宽为470 MHz,y输入端的-3 dB带宽为4.20 GHz的良好结果,整个乘法器电路的功耗为2.82 mW.     

一种高精度带隙基准电压源设计

提出一种采用0．35umCMOS工艺制作的带隙基准电压源电路,该电路具有高电源抑制比和低的温度系数。整体电路使用TSMC0．35umCMOS工艺,采用HSpice进行仿真。仿真结果表明,在-25～＋125℃温度范围内温度系数为6．45ppm／C,电源抑制比达到-101dB,电源电压在2．5～4．5V之间,输出电压Vrel的摆动为0．1mV,功耗为0．815mW．是一种有效的基准电压实现方法。     

基于0.25μm CMOS工艺的1.8V Rail-to-Rail运算放大器

采用TSMC0．25μm CMOS工艺，设计实现了一种低功耗、高增益带有恒跨导输入级的Rail—to—Rail运算放大器。基于BSIM3V3 Spice模型，采用Hspice对整个电路进行仿真，在1．8V的单电源电压工作条件下，直流开环增益达到108．6dB，相位裕度为57．2度，单位增益带宽为5MHz，功耗为0．23mW。     

一种新颖的高性能带隙基准的设计与分析

提出了一种新颖的分段线性补偿带隙基准,该补偿技术通过巧妙地运用带隙输出电压与三极管开启电压VBE的关系来实现.电路设计中,考虑了基准电压的电源抑制特性、线性调整率、电路的稳定性、功耗、芯片面积等各方面的因素,使得该电路很适合工程应用.全电路由BiCMOS工艺实现,并通过HSPICE仿真.结果表明,基准输出电压约1.169 V,有效温度系数仅为2.1×10-6/℃;室温下,电源抑制比为63 dB@1 kHz,功耗70μW(3 V电源).     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.     

Design and application of precise analog computational circuits

New versatile building blocks for implementing analog functional circuits such as a multiplier, a squarer, and a square rooter based on functional terms of a differential input circuit are proposed and implemented in 0.25 um CMOS process. The input range of these circuits is over  ±1.0 V with a high linearity of less than 4% for 3.3 V power supply. The  ?3 dB bandwidth of all discussed circuits has been measured to over 200 MHz. The functional circuit size is 340 μm², and its typical power consumption is about 90 uW.     

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications.     

一种用于THD优化的模拟乘法器设计

为有效地提高有源功率因数校正控制器(APFC)[1]性能,设计了一种用可控电流法实现,可应用于连续/临界型(CCM/DCM)升压(BOOST)模式APFC的模拟乘法器.该乘法器有较好的线性特性,线性范围达到0~3V,与传统方法相比,特别嵌入了总谐波失真(THD)优化电路,从而达到最优化输入电流THD,提高功率因数的目的.最后给出了具体的乘法器电路图和仿真结果.     

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8?×?8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8?×?8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35?μm standard CMOS process.     

A high-speed high-density silicon 8/spl times/8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.     

Low-Voltage BiCMOS Four-Quadrant Multiplier and Squarer

A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 m BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured –3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 W. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.     

Ultra-low-power, class-AB, CMOS four-quadrant current multiplier

A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. Simulation results show that from a 0.65 V supply, the proposed circuit consumes 12.4 nW static power while less than 230 dB total harmonic distortion is achieved for an input modulation index up to 10.     

一种低温漂低功耗的简易带隙基准电压设计

电压基准在模拟电路中提供一个受电源或温度等影响较小的参考电压,以保证整个电路正常工作。设计了一种低温漂低功耗带隙基准电压源,采用不受电源影响的串联电流镜做偏置．利用PTAT电压的正向温度系数和基极发射极电压的负向温度系数特性,以适当的系数加权构造零温度系数的电压量。该设计避开了运放的应用．结构简易,原理清晰,便于入门级的同学在短时间内学习掌握。0-70℃范围内,温漂系数为16．4ppm／℃。供电电压在5-6V范围内变化时,电源抑制比达57．7dB。总输出噪声为140．3μV,功耗为300．6μW。