电路系统中的闩锁效应及其预防设计分析

随着社会的不断发展及经济水平的提升,我国的电力系统也得到极大的发展。然而现阶段我国的电路系统在运行过程中往往会有闩锁效应发生,而这种现象往往会对电路系统的正常运行产生较为严重的影响。文章深入地对电路系统中的闩锁效应进行了分析,并针对这种现象提出了相应的预防设计方案,希望能为电路系统的正常运行提供帮助。     

CMOS电路中的闩锁效应研究

闩锁效应是功率集成电路中普遍存在的问题。文中分析了CMOS结构中的闩锁效应的起因,提取了用于分析闩锁效应的集总器件模型,给出了产生闩锁效应的必要条件,列举了闩锁效应的几种测试方法。最后,介绍了避免发生闩锁效应的几种方法。     

CMOS集成电路闩锁效应抑制技术

闩锁效应是CMOS集成电路在实际应用中失效的主要原因之一,而且随着器件特征尺寸越来越小,使得CMOS电路结构中的闩锁效应日益突出。文章以P阱CMOS反相器为例,从CMOS集成电路的工艺结构出发,采用可控硅等效电路模型,较为详细地分析了闩锁效应的形成机理,给出了闩锁效应产生的三个基本条件,并从版图设计和工艺设计两方面总结了几种抑制闩锁效应的关键技术。     

CMOS结构中的闩锁效应

本文较为详细地阐述了体硅CMOS结构中的闩锁效应，分析了CMOS结构中的闩锁效应的起因，提取了用于分析闩锁效应的集总组件模型，给出了产生闩锁效应的必要条件与闩锁的触发方式。通过分析表明，只要让CMOS电路工作在安全区，闩锁效应是可以避免的，这可以通过版图设计规则和工艺技术，或者两者相结合的各种措施来实现。本文最后给出了防止闩锁效应的关键设计技术。     

一种Bipolar结构中的闩锁效应

闩锁是集成电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致整个器件失效。文章较为详细地阐述了一种Bipolar结构中常见的闩锁效应,并和常见CMOS结构中的闩锁效应做了对比。分析了该闩锁效应的产生机理,提取了用于分析闩锁效应的等效模型,给出了产生闩锁效应的必要条件与闩锁的触发方式。通过对这些条件的分析表明,只要让Bipolar结构工作在安全区,此类闩锁效应是可以避免的。这可以通过版图设计和工艺技术来实现。文章最后给出了防止闩锁效应的关键设计技术。     

CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图、工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应关键技术方案。     

CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。文章首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图设计和工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应的关键技术方案。     

栅极触发PDSOI CMOS闩锁效应研究

测试了不同静态栅极触发电压(输入电压)下诱发CMOS闩锁效应需要的电源电压和输出电压(即将闩锁时的输出电压),发现静态栅极触发CMOS闩锁效应存在触发电流限制和维持电压限制两种闩锁触发限制模式,并且此栅极触发电压.输出电压曲线是动态栅极触发CMOS闩锁效应敏感区域与非敏感区域的分界线.通过改变输出端负载电容,测试出了不同电源电压下CMOS闩锁效应需要的栅极触发电压临界下降沿,并拟合出了0 pF负载电容时的临界下降沿,最终得出了PDSOI CMOS电路存在的CMOS闩锁效应很难通过电学方法测试出来的结论.     

高阻衬底集成电路抗闩锁效应研究

研究用增加多子保护环的方法抑制功率集成电路的闩锁效应,首次给出环距、环宽设计与寄生闩锁触发阈值的数量关系,并比较了不同结深的工序作为多子环的效果.对于确定的设计规则.还比较了不同电阻率衬底材料的CMOS单元中的闩锁效应,结果表明合理设计可以有效地改善高阻衬底的寄生闩锁效应,仿真结果验证了正确性.     

一种高维持电压的LVTSCR

对于工作电压为5 V的集成电路,低压触发可控硅(LVTSCR)的触发电压已能满足ESD保护要求,但其较低的维持电压会导致严重的闩锁效应。为解决闩锁问题,对传统LVTSCR进行了改进,通过在N阱下方增加一个N型重掺杂埋层,使器件触发后的电流流通路径发生改变,降低了衬底内积累的空穴数量,从而抑制了LVTSCR的电导调制效应,增加了维持电压。Sentaurus TCAD仿真结果表明,在不增加额外面积的条件下,改进的LVTSCR将维持电压从2.44 V提高到5.57 V,能够避免5 V工作电压集成电路闩锁效应的发生。     

A better understanding of CMOS latch-up

Both lumped-element two-transistor circuit model and two-dimensional finite-element analyses are used to study the latch-up phenomena in CMOS structures. The equivalent circuit model offers a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up. A generalized criterion for p-n-p-n latch-up is derived based on the equivalent circuit. 2-D modeling confirms the latch-up triggering condition described by the criterion. Furthermore, 2-D simulation models the entire latch-up process, including the dynamic triggering stage, and determines the intrinsic steady-state I - V characteristics of p-n-p-n devices.     

Transient characteristics of latch-up in bulk CMOS

Transient characteristics of the latch-up turn-on process in bulk CMOS are investigated. A measurement technique that evaluates the threshold trigger pulse current of latch-up and also observes latch-up turn-on transient waveforms is established. Through the comparison between experimental data and precise circuit simulation results, the main factors that determine transient latch-up characteristics are clarified as the base-emitter diffusion capacitors.     

对辐射感应闭锁窗口现象的解释

中、大规模CMOS器件受到瞬态辐射时，出现了闭锁单窗口、多窗口现象。为了获得闭锁窗口的出现原因，借助对窗口现象的有关参考文献的研究，利用计算机电路模拟软件，分析了CMOS器件多个闭锁路径之间的相互作用。在此基础上，提出了解释窗口现象的“三径”闭锁模型。应指出的是，该闭锁模型还需要试验上的进一步验证与支持。     

Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period     

Correlations between CMOS latch-up characteristics and substrate structure parameters

A structure-oriented model based on a simplified two-dimensional numerical analysis has been developed to calculate the substrate spreading resistance of a parasitic SCR latch-up path in a CMOS circuit. This model establishes the correlation between the major latch-up characteristics parameters (holding voltage, holding current and triggering current) and the structure parameters in the substrate. The correlations thus obtained have been used to predict the effects of layout and structural changes in the substrate on the latch-up characteristics through the application of this model. It has been verified that the calculated results are in good agreement with both the experimental results of the fabricated devices and the simulation results based on the exact two-dimensional numerical analysis.