一种应用于DSP嵌入式存储器的灵敏放大器设计

提出了一种新型灵敏放大器,电路由单位增益电流传输器、电荷转移放大器及锁存器三部分组成。基于0.18μm标准CMOS单元库的仿真结果表明,与现有几种灵敏放大器相比,新型灵敏放大器具有更低的延时和功耗,在1.8 V工作电压、500 MHz工作频率、80μA输入差动电流以及DSP嵌入式SRAM6T存储单元测试结构下,每个读周期的延迟为728 ps,功耗为10.5fJ。与电压灵敏放大器相比,延迟减少约41%,功耗降低约50%;与常规电荷转移灵敏放大器相比,延迟减少约22%,功耗降低约37%;与WTA电流灵敏放大器相比,延迟减少11%,功耗降低31.8%。     

一种用于嵌入式闪存的低压灵敏放大器(英文)

提出了一种适合于低电压嵌入式闪存的灵敏放大器。该灵敏放大器采用了增强电流感应的方法,使得电源电压可以降到1.5V及其以下。灵敏放大器中采用的动态位线箝位电路可以提高位线预充速度并减小功耗。本电路在0.13μm的Flash工艺中实现。测试结果表明:提出的灵敏放大器在电源电压为1.5V时,访问时间是25ns;在电源电压为1.2V时,访问时间是32ns。     

一种快速、低压的电流灵敏放大器的设计

提出了一种快速和低工作电压的非挥发性存储器的电流灵敏放大器。该电路采用自控恒流预充电路提高灵敏放大器的放大速度。TSMC的0．18μm模型库的HSPICE仿真结果表明，电路在-40℃～125℃范围内有快速的读取速度，在1V工作电压和室温下，电路的读取时间是33ns。     

一种新型的高性能CMOS电流比较器电路

分析了目前几种高性能连续时间CMOS电流比较器的优缺点,提出了一种新型CMOS电流比较器电路．它包含一组具有负反馈电阻的CMOS互补放大器、两组电阻负载放大器和两组CMOS反相器．由于CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗,从而使电压的变化幅度减小,所以该电流比较器具有较短的瞬态响应时间和较快的速度．电阻负载放大器的使用减小了电路的功耗．利用1.2μm CMOS工艺HSPICE模型参数对该电流比较器的性能进行了模拟,结果表明该电路的瞬态响应时间达到目前最快的CMOS电流比较器的水平,而功耗则低于这些比较器,具有最大的速度/功耗比．此外,该CMOS电流比较器结构简单,性能受工艺偏差的影响小,适合应用于高速/低功耗电流型集成电路中．     

一种大规模闪存灵敏放大器的多相位预充方法

随着微电子技术节点不断向前推进,非挥发性存储器(NVM)的容量迅速增大,对读取速度的要求也日益提高。通常,在大规模快闪存储器中采用页读取模式将多个比特的数据同时读取到缓存中,再从缓存中依次输出数据。这样等效于缩短读取周期,但也会遇到瞬态功耗过大的问题。作为改进措施,提出一种新型电流型灵敏放大器的预充方法,在传统灵敏放大器的基础上,采取多相位预充的方法,分时段对位线进行预充电,将瞬态大电流平均到整个预充周期,从而在保证低功耗的同时加大页读取的容量,提高读取速度。经验证,采用该方法的灵敏放大器具有较快的读取速度、较低的功耗,在3.3V工作电压下,电路的读取时间为7ns。     

基于电阻电流镜的低压灵敏放大器设计

提出一种适用于低压快闪存储器的电流模式的低压灵敏放大器.该灵敏放大器在基准电流产生电路中使用电阻电流镜代替传统的晶体管电流镜,使得基准电流产生电路的工作电压减少了一个阈值电压,从而降低灵敏放大器的工作电压.位线电压控制电路中运算放大器的使用减少了由于温度和工艺变化所引起的位线电压变化,进而提高读取操作的精度.采用中芯国际90nm工艺设计,提出的灵敏放大器在1.2V电源电压时的读取时间是14.7ns,相对于传统的结构,单个灵敏放大器的功耗被优化了13%.     

应用于无线传感网络 SOC的低功耗∑△调制器

提出了一种应用于无线传感网络 SOC过采样率（OSR）为128的单环三阶单比特量化∑△调制器．通过采用新型前馈结构,降低了系统对运算放大器性能的要求;通过采用新颖的两级Class A/AB运算放大器实现积分器电路,有效降低了电路的功耗;为了进一步降低电路功耗,对调制器中的第二级、第三级运放进行了缩放．该调制器采用华虹0．18μm CMOS工艺,输入信号带宽为8 kHz ,工作电压1．8V ．后仿真结果表明：在输入信号频率为5 kHz、采样时钟为2．048 M Hz时,调制器的信噪比（SNR）达到96dB ,整个调制器的功耗仅为180μW ,芯片总面积为0．51 mm2．     

一种新型的CMOS电流反馈运算放大器

电流反馈运算放大器在高速高频电子领域有广泛的应用，但目前市场上流行的基于互补双极性结构的电流反馈运算放大器的电源电压和功耗都较高。文章主要在文献[1～3]基础上设计了一种新型的CMOS电流反馈运算放大器，使用0．51μmCMOS工艺参数（阈值电压为0．7V），模拟结果获得了与增益无关的带宽、极大的转换速率。电路参数为：81db的开环增益、87度的相位裕度、123db共模抑制比，以及在1．5V电源电压下产生了约6．2mW的功耗。     

含失调补偿的高速灵敏放大器的设计

灵敏放大器被用于静态随机存储器中数据的读出,该文针对灵敏放大器的灵敏度及响应速度问题,基于锁存器型灵敏放大器结构,通过对电路的失调来源进行推导,提出一种利用线性电流的反馈进行失调补偿的电压型灵敏放大器。该电路采用UMC 65 nm工艺,仿真结果表明,改进后电路的灵敏度为50 mV,后仿延时为47 ps,数据读出延时为139.4 ps,功耗延时积为2.006×10-24J·s,且电路的延时、功耗延时积受PVT影响较小。与传统结构的电路相比,灵敏放大器失调电压标准差降低了48.57%,数据读出时总延时为原来的51.42%。     

一种32位DSP cache存储器设计

在一种DSP指令cache的设计中,采用全定制的设计方法,利用0．25μm的CMOS库设计了cache存储器。利用逻辑努力和分支努力的概念优化设计了译码电路,一方面保证了译码器的速度,另一方面减小系统的功耗。并且根据正反馈原理设计了一种差分灵敏放大器,有效地减小了存储器的功耗。电路工作在100MHz的时钟频率下,读写周期的平均动态功耗为25mW。     

A high-speed sensing scheme for 1T dynamic RAMs utilizing theclamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power     

High-speed sensing scheme for CMOS DRAMs

A significant improvement in sensing speed over the half-V_DD bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V_DD. The 2/3-V_DD sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V_DD sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V_DD sensing with a limited bit-line swing has several distinct advantages over the half-V_DD sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs     

Negative capacitance bus terminator for improving the switching speed of a microcomputer databus

The data transfer speed of a microcomputer bus can be improved by adding an active circuit to the bus. This active circuit amplifies the bus voltage and feeds back to the bus a current which is proportional to the time rate of change of the bus voltage. This circuit effectively adds a negative capacitance to the bus. The practical capacitance canceling capability is limited by the propagation delay time of the operational amplifier in the active circuit. The theory of microcomputer bus structures with negative capacitance including effects of amplifier delay is presented. Typically, an operational amplifier with propagation delay less than one tenth of the bus time constant is required to achieve significant (factor of 2) bus speed improvement. High performance operational amplifiers were used to construct a working model of the negative capacitance bus terminator. The experimental results agree well with the theory.     

A low-power readout circuit for nanowire based hydrogen sensor

This paper presents a fully integrated lock-in amplifier intended for nanowire gas sensing. The nanowire will change its conductivity according to the concentration of an absorbing gas. To ensure an accurate nanowire impedance measurement, a lock-in technique is implemented to attenuate the low frequency noise and offset by synchronous demodulation or phase-sensitive detection (PSD). The dual-channel lock-in amplifier also provides both resistive and capacitive information of the nanowire in separate channels. Measurement results of test resistors and capacitors show a 2% resolution in the resistance range 10-40 kΩ and a 3% resolution in the capacitance range 0.5-1.8 nF. Moreover, a 28.7-32.1 kΩ impedance variation was measured through the lock-in amplifier for a single palladium nanowire that was exposed to a decreasing hydrogen concentration (10% H₂ in N₂ to air). The chip has been implemented with UMC 0.18 μm CMOS technology and occupies an area of 2 mm². The power consumption of the readout circuit is 2 mW from a 1.8 V supply.     

一种用于LCD驱动的低功耗输出缓冲放大器

在AB类输出级的基础上,结合正反馈辅助的B类输出级,提出了一种用于LCD驱动电路的大输出摆率、低功耗的输出缓冲放大器。在0.15μm高压CMOS工艺模型下,该放大器能够驱动0～20nF范围的容性负载,静态电流为7μA,1%精度建立时间小于6μs,满足了LCD驱动电路行建立时间的要求;通过采用共源共栅频率补偿结合输出零点补偿技术,较好地满足了大动态范围容性负载的要求。     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

0.9 V current-mode sense amplifier using concurrent bit- and data-line tracking and sensing techniques

A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It overcomes the long-unattended weaknesses of existing designs simply by forcing the data-lines to track the changes on the bit-lines. It has improved the sensing speed and the power consumption of the best prior art by 202 and 216%, respectively. Furthermore, the new design can operate down to a supply voltage of 0.9 V.     

深亚微米SRAM电流感应电路的分析和优化*

本文对随机掺杂浮动效应下传统的电流感应电路的可靠性做了定量的分析。主要考虑了晶体管尺寸、控制信号的下降时间和特定晶体管的阈值电压三方面对电流感应电路可靠性的影响。在这个基础上,我们做了最终的优化来提高电流灵敏放大器的可靠性。在90纳米工艺下,仿真结果显示最终优化后的电流感应电路的失败率能够比优化前减少百分之八十,而延时只是稍微增加一点。     

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.