一种用于LCD驱动的低功耗输出缓冲放大器

在AB类输出级的基础上,结合正反馈辅助的B类输出级,提出了一种用于LCD驱动电路的大输出摆率、低功耗的输出缓冲放大器。在0.15μm高压CMOS工艺模型下,该放大器能够驱动0～20nF范围的容性负载,静态电流为7μA,1%精度建立时间小于6μs,满足了LCD驱动电路行建立时间的要求;通过采用共源共栅频率补偿结合输出零点补偿技术,较好地满足了大动态范围容性负载的要求。     

A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35?µm CMOS high-frequency model to design a fully integrated 1?V, 5.2?GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50?Ω. The simulation results show that the amplifier provides a gain of 9.48?dB, a noise figure of 4.08?dB, and draws 13.4?mW from a 1?V supply. The S11 and S22 are both lower than ?15?dB.     

Automated bias control (ABC) circuit for high-performance VLSIs

A biasing scheme for sensing circuits, namely an automated bias control (ABC) circuit, for high-performance VLSIs is described. The ABC circuit can automatically gear the output level of sensing circuits to the input threshold voltage of the succeeding CMOS converters. The sensing performance can be accelerated with the ABC circuit either by reducing the excessive signal level margin between the sensing circuits and the CMOS converters or by reducing extra stages of signal amplification. Since feedback control of the ABC circuit ensures correct DC biasing even under large process deviations and circuit condition changes, a wider operation margin can also be obtained. Three successful applications of the ABC circuit are reported: a sense amplifier, an address transition detector (ATD), and an ECL-CMOS input buffer. A 64-kb BiCMOS SRAM employing the proposed sense amplifier and the ATD has been fabricated with a 0.8-μm 9-GHz BiCMOS technology. The SRAM has an address access time of 4.5 ns     

CMOS峰值检测电路

采用差动运算放大器加电流镜的方法,设计了一种CMOS峰值检测电路,包括峰值电压检测及输入信号过峰时刻甄别两部分.该电路设计基于0.5μm CMOS工艺,实现对峰值电压范围为0～5V,脉冲宽度1～5μs的准高斯信号的精确检测,误差小于6mV。另外,改进了过峰时刻甄别电路,采用了先微分再过零比较的办法,避免了一个准高斯信号输出多个峰值电压.     

Programmable switched-capacitor bump equalizer architecture

A versatile and economical switched-capacitor (SC) equalizing structure to compensate attenuation characteristics is presented. The monolithic SC bump equalizer has three operational amplifiers and six capacitor banks to independently control the center frequency, bandwidth, and peak voltage gain steps for the bump (and dip) frequency response. The bump equalizer has been integrated using 3-μm CMOS (p-well) technology and occupies an area of 3.36 mm², including an additional test amplifier and test buffer. The circuit operating from ±5-V power supplies typically dissipates 60 mW when sampled at 75 kHz     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

Design of a New High Speed Amplifier Circuit for the Analog Subsystems

A high speed CMOS amplifier circuit with a new architecture especially suited for analog subsystems and a simple high speed CMOS comparator utilizing the proposed CMOS amplifier circuit are presented. The proposed circuit is simulated using 0.35 m process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended amplifier. Design details and simulation results show that the newly designed CMOS amplifier circuit and the high speed CMOS comparator are applicable to high speed analog subsystems, especially the flash A/D converter.     

A high speed,precision voltage buffer in a submicron CMOS process

A new buffer architecture was introduced by Comer and Comer (1998, International Journal of Electronics, 84, 345). This buffer uses an active feedback network based on a transconductance amplifier. An implementation of the new buffer was done in a CMOS process. The buffer was intended for the output stage of a 10-bit video digital-to-analogue converter. The circuit was fabricated on the American Microsystems 0.6 μm process. Design specifications called for a gain accuracy of 0.1%, an offset voltage shift of no more than 1mV over a commonmode input range of 50% of supply voltage and a bandwidth of 500MHz. The actual circuit showed a gain error of less than 0.1%, a common-mode offset variation of less than 2mV, and a bandwidth of 450MHz.     

A 75 μW rail-to-rail class AB CMOS operational amplifier

A new class AB CMOS operational amplifier featuring rail-to-rail output swing is presented. The proposed circuit operates with an output voltage supply of 1 V only, while the overall power consumption is lower than 75 μW. The output stage shows a quiescent current of 15 μA, while it guarantees a peak current of 220 μA. The slew rate is 1.5 V μs⁻¹ (C₁ = 150 pF) and the THD is −63 dB, when a 0.98 V_pp−10.4 kHz sinewave is applied, as measured on an experimental prototype realised with a standard 0.8 μm CMOS process. The circuit presented is suitable for use in portable hand-set systems or in medical aids.     

A New CMOS Buffer Amplifier Design Used in Low Voltage MEMS Interface Circuits

To achieve low voltage high drivingcapability with quiescent current control, a class-AB CMOS buffer amplifier usingimproved quasi-complementary output stage and error amplifiers with adaptive loadsis developed. Improved quasi-complementary output stage enables it more suitablefor low voltage applications, while adaptive load in error amplifier is used toincrease the driving capability and reduce the sensitivity of the quiescentcurrent to fabrication process variation. The circuit has been fabricated in 0.8μm CMOS process. With 300 Ω load in a ±1.5 V supply, its outputswing is 2.42 V. The mean value of quiescent current for eight samples is 204μA, with the worst deviation of 17%.     

A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier

A 0.9-V 0.5-μA, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode nMOS transistors buffer a bulk-driven pMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low-voltage translinear control circuit     

Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation

The paper presented here offers a two stage amplifier where both stages are in class AB mode. The input stage makes use of a floating gate metal oxide semiconductor (FGMOS) transistor which enables this circuit to operate at lower voltage and also increases overall linearity. The frequency compensation is done using voltage buffer scheme. A super source follower (SSF) acts as voltage buffer and exploited here with a series capacitor. The function of SSF is to enhance phase margin (PM) and gain bandwidth product (GBW) of the amplifier. The small signal equivalent and mathematical analysis of circuit is also given. The performance of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 μm process parameters. The ac simulation results of amplifier show that GBW is 9 MHz and power consumption is 0.5 mW.     

A CMOS differential buffer amplifier with accurate gain andclipping control

A CMOS fully differential buffer amplifier with accurate gain and clipping control is presented. The gain is made variable by controlling the amount of the feedback around the power amplifier by means of an additional gain control loop. A new clipping technique is used to control the clipping level of the amplifier. The amplifier is realized in a 1.2 μm CMOS process with a single 5 V power supply. Measurements confirm the presented techniques     

用于巨磁阻生物传感器检测的模拟前端电路

提出一种用于巨磁阻(GMR)生物传感器检测的模拟前端电路。电路采用电压检测的方法,包括基准电压源,单位增益缓冲器,电荷转移型开关电容采样保持电路,流水线模数转换器四部分;基准电压源用于产生传感器阵列的片内激励电压;传感器阵列的检测输出电压经单位增益缓冲器后,由开关电容采样保持电路进行采样,保持,放大;最后经过流水线模数转换器输出数字码流;芯片采用SMIC 0.18μm 1P6M CMOS厚栅氧工艺实现。测试结果表明,在电源电压3.3 V,20 MHz时钟下测试,整体电路输出信号有效精度达到7.2 bit,功耗33 mW,满足GMR生物传感器的检测要求。     

Robust design of low EMI susceptibility CMOS OpAmp

This paper addresses a new approach to design a CMOS operational amplifier which provides a good tradeoff between high gain and strong immunity to electromagnetic interferences. The proposed amplifier is based on two main blocks: the first is a fully differential folded cascode with modified input pair and the second is a source cross coupled AB class buffer. Thanks to the folded cascode stage and to the symmetrical output buffer, the amplifier exhibits both intrinsic robustness to interferences and good amplifier performances. The circuit was fabricated in a 0.8-/spl mu/m n-well CMOS technology (AMS CYE process). Experimental results, in terms of electromagnetic interference (EMI) immunity, are presented and successfully compared with commercial amplifiers. Measurements carried out on the chip and the amplifier overall performances are provided along with the corresponding simulation results.     

Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks

We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-μm CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of ?47.2 dBm while consuming only 6.8 μW from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.     

Alternative Realizations of CMOS Current Feedback Amplifiers for Low Voltage Applications

Two variants of a new current feedback amplifier (CFA) are presented in this paper. These CFAs are realized in CMOS technology and both are capable of working at low voltages. It is shown that one circuit performs better than the other by virtue of an increased impedance at its Z terminal achieved through the use of additional transistors. Analysis of both variants of the current conveyor and buffer that form the current feedback amplifier gives an insight into the location of primary poles and zeros of the CFAs. Simulation results indicate an overall gain bandwidth product in excess of 59 MHz and 102 MHz for each circuit at a gain of –10 and with a 3.3 V supply. Experimental results from a chip fabricated in a 0.35 m CMOS technology agree closely with the simulation results.     

2 Gbit/s transimpedance amplifier fabricated by 0.35 μm CMOStechnologies

Integrated CMOS transimpedance (TZ) amplifier circuits have been designed and fabricated based on a home-made BSIM model. A 0.35 μm CMOS technology was used for circuit realisation, and a capacitive-peaking design to improve the bandwidth of the TZ amplifier is proposed and investigated. Using this approach provides an easy way to improve the performance of the TZ amplifier; the measured 3 dB bandwidth is enhanced from 875 MHz to 1.35 GHz. The CMOS TZ amplifier design achieves a 2 Gbit/s data rate     

X-band fully depleted SOI Amplifier with adaptive bias control

A 10-GHz amplifier with an adaptive bias control circuit is realized using fully depleted SOI CMOS technology. The effective gate bias of the amplifier MOSFET adjusts itself based on the power level of the input signal. Measured results showed reduction of overall power consumption and wider range of output power near its peak efficiency. At absence of the signal, the amplifier can be automatically switched to a standby mode with approximately 85% reduction of power consumption. Power saving is also demonstrated for pulsed signal modulated at 10 MHz.     

A Low-Power, High-Suppression V-band Frequency Doubler in 0.13 $mu$ m CMOS

A V-band frequency doubler monolithic microwave integrated circuit with a current re-use buffer amplifier is presented. The circuit is designed and fabricated using 0.13 $mu$m CMOS technology. The buffer amplifier uses a current re-use topology, which adopts series connection of two common source amplifiers for low dc power consumption. The suppression of the fundamental frequency is obtained by shunting the input frequency at the output node of the doubler and the drain nodes of two common-source stages of the buffer amplifier. The fabricated frequency doubler exhibits an output power of ${-}$4.45 dBm and a conversion gain of ${-}$ 0.45 dB at input frequency of 27.1 GHz with an input power of ${-}$4 dBm. The suppression of the fundamental signal is 49.2 dB. The total dc power dissipation is 9 mW while the buffer amplifier consumes 5 mW. The integrated circuit size including pads is 1.24 mm$, times ,$0.75 mm. To our knowledge, this is the highest suppression with low-power dissipation among V-band frequency doublers.