A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchicalsquare-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 μm² cell and 581.8 mm² small die area are achieved using 0.15-μm CMOS technology. The ×61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described     

Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit

A new multi-valued static random access memory (MVSRAM) cell with a hybrid circuit consisting of a single-electron (SE) and MOSFETs is proposed. The previously reported MVSRAM with an SE-MOSFET hybrid circuit needs two data lines, one bit line for write operations and one sense line for read operations, to improve the speed of the read-out operation, but the proposed cell has only one data line for read/write operations, resulting in a memory area that is much smaller than that of the previous cell, without any reduction of read-out speed.     

CMOS/SOS memory circuits for radiation environments

Memory circuit techniques which combine radiation hardness with high density, high speed, and low power dissipation have been developed. CMOS/SOS circuits featuring self-compensation, self-biasing, and parameter tracking accommodate a wide range of nonuniform on-chip parameter variations. These variations may occur as the result of exposure to a nuclear radiation event or from MOS device processing, temperature, or power-supply effects. The circuits discussed in this paper are key elements for radiation-hardened memory designs [up to 10/SUP 6/ rad (Si)] with state-of-the-art LSI density and performance. The CMOS/SOS memory cell sizes (3.1 mil/SUP 2/ for a six-device static cell and 2.5 mil/SUP 2/ for a four-device static cell) are nearly five times smaller than previous radiation-hardened cells.     

一种新型Class AB开关电流存储单元的设计

设计了一种新型高性能Class AB开关电流(SI)第一代存储单元电路。电路由对称的电压反转跟随器(FVF)连接Class AB SI存储单元组成,输入级采用电流传输器结构,输出级采用可调共源共栅结构,电路具有误差小、功耗低、性能高等特点。基于此存储单元,设计了延时器和双线性积分器进行验证。电路采用SMIC 0.18μm工艺,在Spectre中进行仿真。结果表明,该存储单元具有较好的性能和应用价值。     

New input/output designs for high speed static CMOS RAM

New input and output schematics and optimum design for cell and array are proposed, and applied to a 256/spl times/4 bit CMOS static RAM. Simplified decoder circuit with effective decoder control circuit has a high speed and a wide timing margin. Simple sense amplifier and compact output circuit bring higher speed and reduction in pattern area. Using p-channel transfer gate for memory cell and array, the switching speed and operational stability are much improved. The device is fabricated by 5 /spl mu/m layout rule Si-gate CMOS technology. An 80 ns access time and 100 ns minimum cycle time are acquired at 5 V supply. Power dissipation is less than 7.5 mW at 1 MHz operation.     

High-density static ESFI MOS memory cells

The area of static MOS memory cells is reduced by avoiding crossovers in the flip-flop, and by selecting the cell by a diode. Such cells have been realized in epitaxial silicon films on insulators (ESFI) with complementary transistors, diodes, and high-rated load resistors; the cell areas can be as small as 1500 /spl mu/m/SUP 2/ (2.4 mil/SUP 2/), and are the smallest areas of static MOS memory cells known so far. The static and dynamic behavior of these cells are discussed, as well as their behavior in a large-scale integrated (LSI) circuit; for this purpose an exploratory memory with 4096 bits and with simple decoding and sensing circuitry has been realized on an area of 3.5/spl times/4.2 mm (140/spl times/170 mils). Taking into account the measured data, an ESFI MOS memory circuit shows a better performance in speed and power dissipation than dynamic MOS memories, but its principal advantage is the static operation mode.     

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells.If we want to reduce the overall power in the memory system,we have to work on the input circuitry of memory architecture i.e.row and column decoder.In this research work,low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed.In this work,the comparison of cluster DECODER,body bias DECODER,source bias DECODER,and source coupling DECODER are designed and analyzed for memory array application.Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool.Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92％ and static energy by 99.92％ at a supply voltage of 1.2 V.The proposed circuit also improves dynamic power dissipation by 5.69％,dynamic PDP/EDP 65.03％ and delay 57.25％ at 1.2 V supply voltage.     

A current-sensed high-speed and low-power first-in-first-out memoryusing a wordline/bitline-swapped dual-port SRAM cell

First-in-first-out (FIFO) data storages are in great demand for telecommunication LSIs. This paper presents high-speed and low-power CMOS memory techniques specialized for FIFO operation. A size-configurable architecture using the tile methodology is employed to customize the word counts and/or data bits with a. short time of less than 30 min. Four flag bits are introduced to inform the internal state of FIFO memories. To obtain a higher operating speed, an SRAM-like memory cell with current-sense readout is used. The critical-path delay of the Gray-code up/down counter, indicating the stored data volume, is shortened to 6.0 ns (66%) by using a double-rail single-stage XOR circuit. As to the low-power techniques, a wordline/bitline-swapped dual-port memory-cell architecture is proposed to cut off the static power-supply current of unselected columns. By using the hidden blanket-precharged bitline scheme, the power dissipation of the writing circuitry is minimized without degrading the operating speed. A new data-driven gated-shift-pulse architecture is also proposed to reduce the power dissipation of shift-register-type address pointers (1.5 mW at 100 MHz). A 2K-words × 8-bits FIFO memory test chip, fabricated with a 0.6-μm CMOS process (a short effective channel length of 0.35 μm is available for both the nMOS and pMOS), has demonstrated the 140-MHz operation at a typical 3.3-V power supply. The power dissipation in standby is less than 0.1 μW and that at 100-MHz dual-port operation with single fan-out loads is in the range from 28 mW (in the best case with the M-scan test pattern) to 46 mW (in the worst case with the checkerboard test pattern)     

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V     

Negative resistance element for a static memory cell based onenhanced surface generation [MOS devices]

A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories     

An optoelectronic CMOS memory circuit for parallel detection andstorage of optical data

A CMOS static RAM (SRAM) circuit capable of detecting and storing optically transmitted data is described. Bits of data are transferred to the memory circuit via an array of parallel light beams. A 16-b optoelectronic SRAM was fabricated in a standard bulk CMOS process and tested using argon and helium-neon lasers. Data contained in an array of 16 light beams with an average power of 3.35 μW/pixel were successfully transferred to the SRAM in parallel fashion. The storage of the optical information was verified by electronically addressing each cell. The optical data transfer technology is extended to other systems in which high speed and parallelism are essential     

Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router

We propose a new CAM architecture for the large-scale integration and low-power operation of a network router application. This CAM reduces entry count by an average of 52%, using a newly developed one-hot-spot block code. This code eliminates redundancy in a memory cell and improves the efficiency of IP address compression. To implement the proposed code, a hierarchical match-line structure and an on-chip entry compression/extraction scheme are introduced. With this architecture, a search-depth control scheme deactivates unnecessary search lines and reduces power consumption by 45%. Using a DRAM cell, our new content addressable memory (CAM) can achieve 1.5 million entries in 0.13-/spl mu/m technology, which is six times more than a conventional static ternary CAM.     

An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup

A static random access memory (SRAM)-based novel hardware architecture for longest prefix match (LPM) search scheme has been proposed in this paper. The key concept of this architecture is to store the IP prefixes virtually in the forwarding table. This architecture reduces memory consumption by using a two-tier hierarchical SRAM-based memory structure for maintaining the next hop port information. Originally, next hop addresses are kept in the shared global memory called next hop global memory (NHGM) and its links are maintained in another memory, called next hop link memory (NHLM). This approximately reduces memory consumption by 50–62.5% compared to existing SRAM-based schemes. The proposed architecture consumes single memory write cycle to store an IP prefix and also takes single memory read cycle for LPM search. However, finding next hop information incurs two memory read cycles due to hierarchical next hop memory structure. The proposed scheme performs an LPM lookup operation in 1.05–1.31 ns in IPv4 and between 1.05 and 1.6 ns in IPv6. This results into LPM search throughput of 950 million lookups per second (MLPS) to 760 MLPS in IPv4 and between 620 and 950 MLPS in IPv6. The average search throughput achievable from this architecture is roughly 850 MLPS in IPv4 and 780 MLPS in IPv6. The numerical results show that this architecture significantly reduces memory requirement, power consumption, and transistor-count/bit requirement.     

A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding

This article presents a parallel architecture for 3-D discrete wavelet transform (3-DDWT). The proposed design is based on the 1-D pipelined lifting scheme. The architecture is fully scalable beyond the present coherent Daubechies filter bank (9,?7). This 3-DDWT architecture has advantages such as no group of pictures restriction and reduced memory referencing. It offers low power consumption, low latency and high throughput. The computing technique is based on the concept that lifting scheme minimises the storage requirement. The application specific integrated circuit implementation of the proposed architecture is done by synthesising it using 65?nm Taiwan Semiconductor Manufacturing Company standard cell library. It offers a speed of 486?MHz with a power consumption of 2.56?mW. This architecture is suitable for real-time video compression even with large frame dimensions.     

High Performance Static Segment On-Chip Memory for Image Processing Applications

The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power and area efficient design without compromising quality in data-intensive computing applications. This paper proposes a design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications. In this static segment method, n-bit data array is reduced by m-bit data array for significant value of input data to achieve balanced design metrics at the cost of accuracy. The proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture for the approximate computing applications. From the overall simulation results, the proposed 4-bit SSOC SP SRAM design provides 49.02% area savings, 50.62% power reduction and 16.92% speed improvement at the cost of 0.64% Peak Signal to Noise Ratio (PSNR) and exhibits same visual quality in comparison with the existing 8-bit conventional on-chip SP SRAM design in the image processing applications.     

Memory-cell design in Josephson technology

Operating principles and criteria for the design of Josephson memory cells are reviewed and the evolution of cell design is retraced to highlight the various constraints imposed by the requirement for high speed, density, large Operating margins, and ease of auxiliary memory circuit design. Two attractive cells have emerged so far. One is a nondestructive readout (NDRO) ring cell for a subnanosecond cache memory chip; the other a destructive readout (DRO) single-flux quantum cell for main memory applications. Both are presently being used as the basis for ongoing design work.     

QDR SRAM控制器的设计与FPGA实现

介绍一种新型静态存储器——QDR（Quad Data Rate）SRAM的存储器结构、与系统的接口连接、主要的操作时序。参考实际QDR存储器内部组成。利用FPGA实现存储器控制器的设计实现。旨在通过FPGA的快速、灵活、容易修改的特点，设计并实现在高速数据通信系统中，QDR静态存储器用于处理器和接口连接的外设之间的数据交换。着重分析QDR控制器的读／写操作状态机。