Artificial Dielectric Shields forIntegrated Transmission Lines

We present a novel shielding method for on-chip transmission lines built on conductive silicon substrates. The shield consists of an artificial dielectric with a very high in-plane dielectric constant, built from two patterned metal layers isolated by a very thin dielectric film. Inserted below an integrated coplanar transmission line, the artificial dielectric layer blocks the electric field of the line from entering the silicon substrate. Shielded coplanar waveguides fabricated on a conventional silicon wafer show a two- to three-fold loss reduction compared to unshielded lines at frequencies below 30 GHz.     

3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-$mu$ m-thick parylene-N layer and 0.56 dB/mm for a 50- $Omega$ CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with underpasses that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-$mu$ m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of ${+}$ 4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.      

硅衬底上共面线的特性及应用

基于理论和实验结果对深亚微米硅集成电路中的共面传输线的特性进行了研究,提出了硅衬底上传输线分布参数的提取方法和减小共面线衰减的一些设计准则.成功地将共面线应用在深亚微米高速集成电路的设计中,并给出了放大器芯片和共面线的测试结果.测试结果表明:在深亚微米CMOS高速集成电路中,用共面线实现电感是一种行之有效的方法.     

Millimeter-wave CMOS design

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in today's mainstream CMOS technologies.     

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $mu$m CMOS Process

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 $mu$m CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.      

60 GHz CMOS pulse generator

A 60 GHz CMOS pulse generator (PG) is presented for the wireless transmission of uncompressed HDTV data, and is realised by only CMOS transistors. The CMOS PG was fabricated using a 90 nm CMOS process with nine metal layers. A carrier frequency of 62.5 GHz was obtained at a supply voltage of 1.15 V with an output power of -25 dBm. The power consumption was 11.5 mW at 1.5 GHz input frequency     

W-band finite ground coplanar monolithic multipliers

This paper describes the design, fabrication, and experimental evaluation of W-band planar monolithic varactor frequency multipliers based on finite ground coplanar (FGC) lines. These lines are a low-loss low-dispersion alternative of a planar transmission line to more conventional microstrip of coplanar waveguide lines at millimeter-wave frequencies. The near transverse-electromagnetic nature of propagation of the FGC lines simplifies circuit design and layout. Two-diode W-band varactor multipliers with input Q's of two and three and FGC input and output have been realized. The multiplier with input Q=2 has an output power of 72 mW, an efficiency of 16.3% near 80 GHz, and a -3-dB bandwidth greater than 10 GHz, while the multiplier with Q=3 has an efficiency of 21.5% near 70 GHz and a 6-GHz bandwidth. This paper briefly describes the characteristics of the FGC lines, the design of the multipliers and their radiofrequency performance     

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.     

Low-loss on-chip transmission lines with micro-patterned artificial dielectric shields

Low-loss coplanar waveguide (CPW) transmission lines integrated on a standard (5 -10 Omega ldr cm) silicon substrate are realised by using an artificial dielectric shield with a very high in-plane dielectric constant. The shield consists of a 30 nm-thick Al₂O₃ film sandwiched by two 100 nm-thick aluminium layers patterned into lattices of mum-size elements. The individual metallic elements are micro-patterned to suppress the flow of eddy currents at microwave frequencies. Inserted below the CPW, the shield blocks the electric field of the line from entering the silicon substrate. The resulting line attenuation (measured up to 25 GHz) is comparable to that of identical CPWs built on a high-resistivity silicon wafer.     

Analysis and Design of a Chip Filter With Low Insertion Loss and Two Adjustable Transmission Zeros Using 0.18- $mu{hbox{m}}$ CMOS Technology

This paper presents the structure of a high-selectivity bandpass filter that is fabricated on low-resistivity silicon substrate with a commercial CMOS technology. The filter is constructed using crossed coplanar waveguide (CPW) lines and metal–insulator–metal capacitors to ensure that it has the desired passband characteristics. An adjustable capacitor between the input and output ports is employed to form a capacitive cross-coupled path, yielding two transmission zeros in the lower and upper stopbands, respectively. Additionally, the coupling mechanism can be modified by turning on or off the gate of an nMOS transistor to adjust the positions of the transmission zeros by applying an externally controlled voltage. To obtain a low passband loss and to minimize the chip size, high-impedance CPW transmission lines are adopted. Our analysis indicates that the CPW line possesses more advantages than the preferred stacked-ground CPW line for constructing the proposed filter. A very compact $X$ -band experimental prototype with a size of ${hbox{0.88}}times {hbox{0.54}} {hbox{mm}}^{2}$ was designed and fabricated. The measurements reveal an insertion loss of less than 3.2 dB in the passband, which is from 10.6 to 12.7 GHz, and rejection levels greater than 35 dB at the designed frequencies of transmission zeros. Moreover, the lower and upper transmission zeros can be shifted from 5 to 6.5 GHz and from 18 to 21.4 GHz, respectively, by changing the controlled voltage.      

A SOI-RF-CMOS technology on high resistivity SIMOX substrates formicrowave applications to 5 GHz

A silicon-on-insulator (SOI) RF complementary metal-oxide-semiconductor (CMOS) technology for microwave applications up to 5 GHz has been developed. The technology is based on ultra large scale integration (ULSI) CMOS processing using a high resistivity separation through implanted oxygen (SIMOX) substrate of typically 10 kΩcm. Dedicated RF n-channel and RF p-channel MOSFET's with an effective channel length of 0.20 and 0.40 μm have been fabricated using a multiple gate finger design. Maximum frequencies of operation f _max of 46 GHz (NMOS) and 16 GHz (PMOS) have been measured. Metal-Insulator-Metal (MIM) capacitances with up to 63 pF with 70 nF/cm ², planar inductances with up to 25 nH and a quality factor up to 12 and coplanar waveguides with a loss <2.8 dB/cm at 5 GHz are monolithically integrated in the technology without additional processes and materials. Using this SOI-CMOS technology we have fabricated integrated silicon RF circuits, e.g., amplifiers, oscillators, and mixers, operating in the 2 GHz range     

2.4 GHz ISM-Band Receiver Design in a 0.18 μm Mixed Signal CMOS Process

This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm².     

基于硅氧化层的嵌入式传输线制造

在有损耗的硅衬底上试制了传输线(微带以及共面波导),并嵌入在CMOS Cu/SiO2互连层中.对传输线的几何尺寸与其特征阻抗、损耗以及衰减因子进行了研究.结果表明嵌入在硅氧化层中的微带和共面波导可以在有损耗的硅片上低损耗地实现,为在硅片上设计微波和毫米波电路提供了必要的无源器件.     

CMOS 0.13 μm共面波导建模与特性分析

基于TSMC0.13μmCMOS工艺,对深亚微米硅基上的共面波导特性进行了研究。在分析中引入了保角映射等数值方法,给出了有效介电常数εeff、特征阻抗Z、单位电容C等传输线指标随几何参数变化的计算公式。并设计了特征阻抗分别为50Ω和70Ω的共面波导传输线元件库。采用Short-Open-Load-Thru(SOLT)校准测试技术对片上传输线元件库进行测试。在0.1~40GHz范围内,测试结果与数值分析解吻合。这为在硅基上进行RFIC设计提供了一个合理选取传输线结构的方法。     

Crosstalk between finite ground coplanar waveguides over polyimide layers for 3-D MMICs on Si substrates

Finite-ground coplanar (FGC) waveguide lines on top of polyimide layers are frequently used to construct three-dimensional Si-SiGe monolithic microwave/millimeter-wave integrated circuits on silicon substrates. Requirements for high-density, low-cost, and compact RF front ends on silicon can lead, however, to high crosstalk between FGC lines and overall circuit performance degradation. This paper presents theoretical and experimental results and associated design guidelines for FGC line coupling on both highand low-resistivity silicon wafers with a polyimide overlay. It is shown that a gap as small as 6 /spl mu/m between two adjacent FGC lines can reduce crosstalk by at least 10 dB, that the nature of the coupling mechanism is not the same as with microstrip lines on polyimide layers, and that the coupling is not dependent on the Si resistivity. With careful layout design, isolation values of better than -30 dB can be achieved up to very high frequencies (50 GHz).     

A New Loss Compensation Technique for CMOS Distributed Amplifiers

This brief presents a circuit technique to compensate for the metal and substrate loss of the on-chip transmission lines (TLs), and, consequently, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). An eight-stage DA suitable for 40-Gb/s optical communication is devised and implemented in a 0.13- $muhbox{m}$ CMOS process. The DA achieves a flat gain of 10 dB from dc to 44 GHz with an input and output matching better than $-$ 8 dB. The measured noise figure varies from 2.5 to 7.5 dB with the amplifier's band. The proposed DA dissipates 103 mW from two 1-V and 1.2-V dc supplies.      

0.13μm CMOS上接地板宽度有限共面波导的特性与建模

讨论了利用TSMC 0.13μm CMOS工艺实现的共面波导的特性及其建模.通过Momentum等电磁场仿真软件计算了传输线的基本参数,例如特征阻抗和衰减常数.并设计了特征阻抗分别为30,50,70和100Ω的共面波导传输线元件库.最后,在0.1～40GHz的范围内利用网络分析仪和SOLT(short-open-load-thru)测试技术测得特征阻抗和衰减常数,共面波导的分布参数则通过提取测试得到的S参数得到.     

A compact planar ultra-wideband bandpass filter with multiple resonant and defected ground structure

A compact bandpass filter with dumbbell shape Defected Ground Structure (DGS) operating on ultra wide pass band (UWB – 3.1 to 10.6 GHz) is proposed. It is based on hybrid microstrip coplanar waveguide (dual sided metal) structure. A Multiple Resonant Structure (MRS) is constructed using coplanar waveguide (CPW) planar transmission line. The MRS makes the resonance using quarter wavelength and half wavelength open-ended CPW. The equispaced three resonances at lower (3.1 GHz), center (6.85 GHz) and higher edge (10.6 GHz) of the whole Ultra Wide Band is achieved using CPW MRS. To make the band as flat as possible, two more resonances are introduced using quarter wavelength microstrip patches on top of the commonly shared substrate, so the proposed filter becomes a five pole bandpass filter. A dumbbell shaped defected ground structure on either side of CPW MRS improves the return loss almost less than 20 dB over the whole UWB passband. The simulated results of proposed filter show good transmission response within passband and good rejection in out of the band. The simulated and measured results are very close to each other which proves the efficacy of proposed design.     

A 7-dB 43-GHz CMOS Distributed Amplifier on High-Resistivity SOI Substrates

This paper presents designs and measurements of distributed amplifiers (DAs) processed on a 130-nm silicon-on-insulator CMOS technology on either standard-resistivity (10 Omegamiddotcm) or high-resistivity (>1 kOmegamiddotcm) substrates, and with either body-contacted (BC) or floating-body (FB) MOSFETs. Investigations have been carried out to assess the impact of active device performance and transmission line losses on circuit design by means of simulations, analytical calculations, and comparisons of the small-signal equivalent-circuit parameters. On standard-resistivity substrates, DAs with FB devices and lossy microstrip lines on thin film exhibit a measured gain of 7.1 dB and a unity-gain bandwidth (UGB) of 27 GHz for a dc power consumption of 57 mW. With the introduction of high-resistivity substrates, other DAs, with the same architecture and using lower loss coplanar waveguide lines, show a UGB of 51 GHz with FB devices and 47 GHz with BC devices. To the authors' knowledge, the designs presented in this paper achieve the best tradeoffs in terms of gain, bandwidth, and power consumption for CMOS-based circuits with comparable architecture.     

High-Performance Slow-Wave Transmission Lines With Optimized Slot-Type Floating Shields

A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide substrate shielding and to shorten the electromagnetic (EM) propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length (SL), strip spacing (SS), and metal layer position of the slot-type floating shields. Wavelength shortening needs to be achieved with a tradeoff between slow-wave effect and attenuation loss. The slot-type floating shields with different SLs, SSs and metal layer positions are analyzed. It is concluded that minimum SL provides the most optimal result. A design guideline can be established to enable circuit designers to reach the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45-nm CMOS process technology. Both measurement and EM waves simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half- or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines.