Unequal Error Protection: An Information-Theoretic Perspective

An information-theoretic framework for unequal error protection is developed in terms of the exponential error bounds. The fundamental difference between the bit-wise and message-wise unequal error protection ( UEP) is demonstrated, for fixed-length block codes on discrete memoryless channels (DMCs) without feedback. Effect of feedback is investigated via variable-length block codes. It is shown that, feedback results in a significant improvement in both bit-wise and message-wise UEPs (except the single message case for missed detection). The distinction between false-alarm and missed-detection formalizations for message-wise UEP is also considered. All results presented are at rates close to capacity.      

Noncoherent Synchronization of UWB-IR Multiple-Antenna Multipath Channels

This paper deals with the maximum-likelihood (ML) noncoherent data-aided (e.g., no blind) synchronization of multiple-antenna ultrawideband impulse-radio (UWB-IR) terminals that operate over broadband channels and are affected by multipath fading with a priori unknown number of paths and path-gain statistics. The synchronizer that we developed achieves the ML data-aided joint estimate of the number of paths and their arrival times (e.g., time delays), without requiring any a priori knowledge and/or a posteriori estimate of the amplitude (e.g., module and sign) of the channel gains. The ultimate performance of the proposed synchronizer is evaluated (in closed form) by developing the corresponding CramÉr–Rao bound (CRB), and the analytical conditions for achieving this bound are provided. The performance gain for the synchronization accuracy of multipath-affected UWB-IR signals arising from the exploitation of the multiple-antenna paradigm is (analytically) evaluated. Furthermore, a low-cost sequential implementation of the proposed synchronizer is detailed. It requires an all-analog front-end circuitry composed of a bank of sliding-window correlators, whose number is fully independent from the number of paths comprising the underlying multiple-antenna channel. Finally, the actual performance of the proposed synchronizer is numerically tested under both the signal acquisition and tracking operating conditions.      

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits

Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66$times$ average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-$mu$ m process.      

Buffered Cross-Bar Switches, Revisited: Design Steps, Proofs and Simulations Towards Optimal Rate and Minimum Buffer Memory

Regarding the packet-switching problem, we prove that the weighed max-min fair service rates comprise the unique Nash equilibrium point of a strategic game, specifically a throughput auction based on a “least-demanding first-served” principle. We prove that a buffered crossbar switch can converge to this equilibrium with no pre-computation or internal acceleration, with either randomized or deterministic schedulers, (the latter with a minimum buffering of a single-packet per crosspoint). Finally, we present various simulation results that corroborate and extend our analysis.      

Novel Scheme for Joint Estimation of SNR, Doppler, and Carrier Frequency Offset in Double-Selective Wireless Channels

As receiver performance will be degraded by carrier frequency offset (CFO), Doppler shift, and low signal-to-noise ratio (SNR), a novel estimator that jointly considers CFO, Doppler shift, and SNR is proposed in this paper. The proposed algorithm uses the Fourier transform (FT) to calculate the power spectral density of time-varying channels through channel estimates. Then, a new periodogram technique is utilized to estimate CFO, Doppler shift, and SNR together. Unlike conventional methods in sinusoid estimation, which rely on the peak-value search of a periodogram, this paper exploits the hypothesis test to address the random frequency modulation of time-varying channels. Furthermore, to optimize estimation performance, a theoretical analysis is also provided on the influences of some key parameters, e.g., the length of the signal processed with fast FT , the amplitude threshold value, the SNR dynamic range, and the velocity dynamic range. Correspondingly, the appropriate key parameters are chosen according to this analysis and are validated by simulations. The results are consistent with our analysis and present high accuracy over a wide range of velocities and SNRs.      

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults

Instead of the traditional spare row/column redundancy architectures, block-based redundancy architectures are proposed in this paper. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column-block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundancy architecture, a heuristic modified essential spare pivoting (MESP) algorithm suitable for built-in implementation is also proposed. According to experimental results, the area overhead for implementing the MESP algorithm is very low. Due to efficient usage of redundancy, the manufacturing yield, repair rate, and reliability can be improved significantly.      

Universal FIR MMSE Filtering

We consider the problem of causal estimation, i.e., filtering, of a real-valued signal corrupted by zero mean, time-independent, real-valued additive noise, under the mean-squared error (MSE) criterion. We build a universal filter whose per-symbol squared error, for every bounded underlying signal, is essentially as small as that of the best finite-duration impulse response (FIR) filter of a given order. We do not assume a stochastic mechanism generating the underlying signal, and assume only that the variance of the noise is known to the filter. The regret of the expected MSE of our scheme is shown to decay as $O(log n/n)$, where $n$ is the length of the signal. Moreover, we present a stronger concentration result which guarantees the performance of our scheme not only in expectation, but also with high probability. Our result implies a conventional stochastic setting result, i.e., when the underlying signal is a stationary process, our filter achieves the performance of the optimal FIR filter. We back our theoretical findings with several experiments showcasing the potential merits of our universal filter in practice. Our analysis combines tools from the problems of universal filtering and competitive on-line regression.      

Modeling of Distributed RLC Interconnect and Transmission Line via Closed Forms and Recursive Algorithms

This paper presents the closed forms of the state-space models and the recursive algorithms of the transfer function models for fast and accurate modeling of the distributed RLC interconnect and transmission lines, which may be evenly or unevenly distributed. Considered models include the distributed RLC interconnect lines with or without external source and load connection. The effective closed forms and recursive algorithms do not involve any matrix inverse, LU matrix factorization, or matrix multiplication, thus reducing the computation complexity dramatically. Especially, the computation complexity of the closed forms for any evenly or unevenly distributed RLC interconnect line circuits is only O(1) or $ { O}(m)$, respectively, in sense of the scalar multiplication times, where $ { m}ll{ N}$ of the system order. The features of new recursive algorithms are two recursive s-polynomials and the low computation complexity. Examples illustrate the new methods in both time and frequency domains. Comparing with the PSpice, the new methods can dramatically reduce the runtime of the time responses and the Bode plots by 25% – 98.5% in the examples. The results can be applied to the RLC interconnect analysis and model reduction as a key to new approach.      

Message Scheduling for the FlexRay Protocol: The Static Segment

In recent years, time-triggered communication protocols have been developed to support time-critical applications for in-vehicle communication. In this respect, the FlexRay protocol is likely to become the de facto standard. In this paper, we investigate the scheduling problem of periodic signals in the static segment of FlexRay. We identify and solve two subproblems and introduce associated performance metrics: 1) The signals have to be packed into equal-size messages to obey the restrictions of the FlexRay protocol, while using as little bandwidth as possible. To this end, we formulate a nonlinear integer programming (NIP) problem to maximize bandwidth utilization. Furthermore, we employ the restrictions of the FlexRay protocol to decompose the NIP and compute the optimal message set efficiently. 2) A message schedule has to be determined such that the periodic messages are transmitted with minimum jitter. For this purpose, we propose an appropriate software architecture and derive an integer linear programming (ILP) problem that both minimizes the jitter and the bandwidth allocation. A case study based on a benchmark signal set illustrates our results.      

Robust Precoder Adaptation for MIMO Links With Noisy Limited Feedback

In this paper, we propose two robust limited feedback designs for multiple-input multiple-output (MIMO) adaptation. The first scheme, namely, the combined design jointly optimizes the adaptation, CSIT (channel state information at the transmitter) feedback as well as index assignment strategies. The second scheme, namely, the decoupled design, focuses on the index assignment problem given an error-free limited feedback design. Simulation results show that the proposed framework has significant capacity gain compared to the naive design (designed assuming there is no feedback error). Furthermore, for large number of feedback bits $C_{rm fb}$, we show that under two-nearest constellation feedback channel assumption, the MIMO capacity loss (due to noisy feedback) of the proposed robust design scales like ${cal O}(P_e2^{-{{C_{rm fb}}over{t+1}}})$ for some positive integer $t$. Hence, the penalty due to noisy limited feedback in the proposed robust design approaches zero as $C_{rm fb}$ increases.      

Normalized LMS Adaptive Cancellation of Self-Image in Direct-Conversion Receivers

This paper presents an adaptive digital signal processing technique that cancels self-image interference due to frequency-independent, in-phase/quadrature-phase (I/Q) mismatch in zero-intermediate frequency (IF) direct-conversion receivers. The proposed technique, which is referred to as the normalized least-mean square adaptive self-image cancellation (NLMS-ASIC) algorithm, is an ASIC technique that controls the filter weight to minimize the power of the filter output signal using an NLMS type of weight-control mechanism. Some closed-form equations are derived for the mean-squared error (MSE), as well as the mean image-rejection ratio (IRR) of the proposed NLMS-ASIC algorithm. In particular, a step-size determination method is explained so that the requirements on the image-rejection performance and convergence time can be satisfied. The advantages of the proposed technique are demonstrated through computer simulations.      

Analysis of Two Alternative ADI-FDTD Formulations for Transverse-Electric Waves in Lossy Materials

A numerical dispersion analysis of the alternating-direction implicit finite-difference time-domain method for transverse-electric waves in lossy materials is presented. Two different finite-difference approximations for the conduction terms are considered: the double-average and the synchronized schemes. The numerical dispersion relation is derived in a closed form and validated through numerical simulations. This study shows that, despite its popularity, the accuracy of the double-average scheme is sensitive to how well the relaxation-time constant of the material is resolved by the time step. Poor resolutions lead to unacceptably large numerical errors. On the other hand, for good conductors, the synchronized scheme allows stability factors as large as 100 to be used without deteriorating the accuracy significantly.      

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.      

A Control Strategy for Four-Switch Three-Phase Brushless DC Motor Using Single Current Sensor

A control strategy based on single current sensor is proposed for a four-switch three-phase brushless dc (BLDC) motor system to lower cost and improve performance. The system's whole working process is divided into two groups. In modes 2, 3, 5, and 6, where phase c works, phase- c current is sensed to control phases a and b, and phase-c current is consequently regulated. In modes 1 and 4, the combination of four suboperating modes for controlling phase-c current is proposed based on detailed analysis on the different rules that these operating modes have on phase-c current. Phase-c current is maintained at nearly zero level first, and phase- a and phase-b currents are regulated by speed circle. To improve control performance, a single-neuron adaptive proportional–integral (PI) algorithm is adopted to realize the speed regulator. Simulation and experimental systems are set up to verify the proposed strategy. According to simulation and experimental results, the proposed strategy shows good self-adapted track ability with low current ripple and strong robustness to the given speed reference model. Also, the structure of the drive is simplified.      

Perceptual Color Image Coding With JPEG2000

A perceptual color image coder (PCIC) is presented for the $YC_{b}C_{r}$ color space within the framework of JPEG2000. This coder employs a vision model based perceptual distortion metric (PDM) to approximate perceived error for rate-distortion (R-D) optimization in order to maximize the visual quality of coded images. The vision model employed in the PCIC is structurally based on an existing monochromatic multichannel vision model, which is extended for color image coding. Subjective tests with 30 viewers show that the PCIC provides superior picture quality at low to intermediate bitrates in comparison with a JPEG2000 compliant coder employing the mean squared error (MSE) and the visual distortion metric (Cvis) as distortion measures, respectively.      

Single-Exclusion Number and the Stopping Redundancy of MDS Codes

For a linear block code ${cal C}$, its stopping redundancy is defined as the smallest number of check nodes in a Tanner graph for ${cal C}$, such that there exist no stopping sets of size smaller than the minimum distance of ${cal C}{bf .},$ Schwartz and Vardy conjectured that the stopping redundancy of a maximum-distance separable (MDS) code should only depend on its length and minimum distance.      

Distributed Throughput Maximization in Wireless Mesh Networks via Pre-Partitioning

This paper considers the interaction between channel assignment and distributed scheduling in multi-channel multi-radio Wireless Mesh Networks (WMNs). Recently, a number of distributed scheduling algorithms for wireless networks have emerged. Due to their distributed operation, these algorithms can achieve only a fraction of the maximum possible throughput. As an alternative to increasing the throughput fraction by designing new algorithms, we present a novel approach that takes advantage of the inherent multi-radio capability of WMNs. We show that this capability can enable partitioning of the network into subnetworks in which simple distributed scheduling algorithms can achieve 100% throughput. The partitioning is based on the notion of Local Pooling. Using this notion, we characterize topologies in which 100% throughput can be achieved distributedly. These topologies are used in order to develop a number of centralized channel assignment algorithms that are based on a matroid intersection algorithm. These algorithms pre-partition a network in a manner that not only expands the capacity regions of the subnetworks but also allows distributed algorithms to achieve these capacity regions. We evaluate the performance of the algorithms via simulation and show that they significantly increase the distributedly achievable capacity region. We note that while the identified topologies are of general interference graphs, the partitioning algorithms are designed for networks with primary interference constraints.      

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

Modern portable embedded devices require processors that can provide sufficient performance for demanding multimedia and wireless applications. At the same time they have to be flexible to support a wide range of products and extremely energy efficient to provide a long battery life. Coarse Grained Reconfigurable Architectures (CGRAs) potentially meet these constraints by providing a mix of flexible computational resources and large amounts of programmable interconnect. The vast design space of CGRAs complicates the development of optimized processors. Most effort has been spent on improving the performance. However, the energy cost of the programmable interconnect is becoming more expensive and this cost can no longer be neglected. In this work we present an energy- and performance-aware exploration for the interconnect of a CGRA and show that important tradeoffs can be made for those metrics. This will enable designers to develop more efficient architectures, tuned to a targeted application domain.      

NetQuest: A Flexible Framework for Large-Scale Network Measurement

In this paper, we present NetQuest, a flexible framework for large-scale network measurement. We apply Bayesian experimental design to select active measurements that maximize the amount of information we gain about the network path properties subject to given resource constraints. We then apply network inference techniques to reconstruct the properties of interest based on the partial, indirect observations we get through these measurements.      

SEChecker: A Sequential Equivalence Checking Framework Based on ${K}$th Invariants

In recent years, considerable research efforts have been devoted to utilizing circuit structural information to improve the efficiency of Boolean satisfiability (SAT) solving, resulting in several efficient circuit-based SAT solvers. In this paper, we present a sequential equivalence checking framework based on a number of circuit-based SAT solving techniques as well as a novel invariant checker. We first introduce the notion of $k$th invariants. In contrast to the traditional invariants that hold for all cycles, $k$ th invariants are guaranteed to hold only after the $k$th cycle from the initial state. We then present a bounded model checker (BMChecker) and an invariant checker (IChecker), both of which are based on circuit SAT techniques. Jointly, BMChecker and IChecker are used to compute the $k$th invariants, and are further integrated in a sequential circuit SAT solver for checking sequential equivalence. Experimental results demonstrate that the new sequential equivalence checking framework can efficiently verify large industrial designs that cannot be verified by existing solutions.