Planar defects in 4H-SiC PiN diodes

Using plan-view transmission electron microscopy (PVTEM), we have identified stacking faults (SFs) and planar defects in 4H-SiC PiN diodes subjected to electrical bias. Our observations suggest that not all planar defects seen in the PiN diodes are SFs. By performing diffraction-contrast imaging experiments using TEM, we can distinguish SFs from other planar defects. In addition, high-resolution TEM (HRTEM) imaging and analytical TEM have revealed that some planar defects consist of a 3-nm-wide SiC amorphous layer. Many of these planar defects are orientated parallel to {1 00} planes, whereas others are roughly parallel to the (0001) plane. The appearance of these planar defects suggests that they are grain boundaries.     

Stacking-fault formation and propagation in 4H-SiC PiN diodes

Stacking-fault growth in SiC PiN diodes has been examined using light-emission imaging and stressing at 80 A/cm² and 160 A/cm². Dark areas in the emission develop because of stacking faults and the current capability of the diode drops. More detailed images are produced by reducing the current by a factor of 1000. The low-current images are bright lines at dislocations bounding the stacking faults and at or near the stacking-fault intersection with the surface. Stacking faults nucleate 1–2 μm below the surface. Most, but not all, continue growing until they span the diode. Growth dynamics and their dependence on the current density are discussed. An erratum to this article is available at .     

High-voltage 4H-SiC PiN diodes with the etched implant junction termination extension

This paper presents the design and fabrication of an etched implant junction termination extension(JTE) for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices.     

Preferential etching of dislocations and stacking faults in gallium phosphide

A combination of optical microscopy and transmission electron microscopy has been used to provide direct evidence that pits formed by the action of a solution of 3 HF:1 H₂O₂ on epitaxial and substrate GaP material close to the (001 ) orientation are associated with dislocations. The formation of different pit shapes can be correlated with previous work on etch pits in GaP, namely the formation of D and S pits. Grooves have been produced on certain crystallographic orientations which are associated with certain types of stacking faults. It is now possible to use this etch for a direct count of the dislocation density in (001) GaP and to indicate the extent of stacking faults.     

Drift-free 10-kV, 20-A 4H-SiC PiN diodes

As impressive as the advancement in 4H-SiC material quality has been, 4H-SiC PiN diodes continue to suffer from irreversible, forward-voltage instabilities. In this work, we describe PiN diodes designed to block 10 kV and conduct 20 A at less than 4.5 V, which were fabricated on 4H-SiC PiN epitaxial layers that were grown with an innovative epitaxial process that has been developed specifically to suppress V_F drift. The diodes fabricated on epitaxial layers that implemented this new epitaxy process showed excellent V_F stability, with 86% of the diodes drifting less than 0.1 V during forward current stressing at 10 A (50 A/cm²) for 30 min. However, these improvements in V_F drift come with a cost in blocking yield, as the surface morphology and other crystal defects imparted by the epitaxial process resulted in only 1 of 50 diodes reaching the 10-kV blocking specification. Nevertheless, the remarkable progress in V_F drift yield brings us closer to commercialization of high-power 4H-SiC PiN diodes.     

Thermal Annealing and Propagation of Shockley Stacking Faults in 4H-SiC PiN Diodes

Stacking faults within 4H-SiC PiN diodes are known to be detrimental to device operation. Here, we present electroluminescence (EL) images of 4H-SiC PiN diodes providing evidence that electrically and optically stimulated Shockley stacking fault (SSF) propagation is a reversible process at temperatures as low as 210°C. Optical beam induced current (OBIC) images taken following complete optical stressing of a PiN diode and that lead to a small number of completely propagated SSFs provide evidence that such defects propagate across the n–/p+ interface and continue to grow throughout the p+ layer. These observations bring about questions regarding the validity of the currently accepted driving force mechanism for SSF propagation.     

基于一种可靠非均匀场限环终端结构的1.4kV 4H型碳化硅PiN二极管

This paper presents the design and fabrication of an effective, robust and process-tolerant floating guard ring termination on high voltage 4H-SiC PiN diodes. Different design factors were studied by numerical simulations and evaluated by device fabrication and measurement. The device fabrication was based on a 12 μm thick drift layer with an N-type doping concentration of 8 × 10^15 cm^-3. P^＋ regions in the termination structure and anode layer were formed by multiple aluminum implantations. The fabricated devices present a highest breakdown voltage of 1.4 kV, which is higher than the simulated value. For the fabricated 15 diodes in one chip, all of them exceeded the breakdown voltage of 1 kV and six of them reached the desired breakdown value of 1.2 kV.     

Study on stacking faults and microtwins in wide bandgap II-VI semiconductor heterostructures grown on GaAs

ZnMgSSe and ZnSSe layers grown on GaAs substrates with GaAs buffer layers by molecular beam epitaxy have been examined by transmission electron microscopy (TEM). The depth level at which paired triangular stacking faults are nucleated in the ZnMgSSe/GaAs heterostructure has been investigated by using the plan-view TEM technique. It has been found that in the ZnMgSSe/GaAs heterostructure the nucleation of the paired stacking faults occurs within a range of depth which starts at the II-VI/GaAs interface and ends at a level that is above the interface by about 120 nm. The dominant type of defects in ZnSSe layers, which have the single triangular shape, has been identified to be microtwins by high resolution TEM.     

碳化硅MPS:新一代功率开关二极管

碳化硅MPS(Merged PiN Schottky diode)具有很好的开关特性，并具有PiN二极管高阻断电压、低漏电流和SBD小开启电压，大导通电流以及高开关速度的优点，是最有希望的新一代功率开关二极管。文章系统地介绍了碳化硅MPS的结构和性能。理论和实验分析表明，碳化硅材料的优异性能与MPS结构的优势相结合，是当今功率开关管发展的趋势。     

Analysis of bulk and surface components of leakage current in 4H-SiC PiN MESA diodes

The leakage current in circular- and ring-shaped epitaxial 4H-SiC PiN mesa diodes with different size and periphery to area ratios was evaluated under the influence of the UV irradiation and temperature in the range from room temperature (RT) to 250 °C. The surface leakage current component was found to dominate the reverse current characteristics and was found to be dependent on time and temperature both after reactive ion etching (RIE) of the diodes in the SF₆/Ar gas mixture and after the UV irradiation. Charging of the surface states is believed to be responsible for the observed behavior. The UV irradiation is believed to charge the surface positively. The drift of the I(V) characteristics is due to the trapping of the electrons neutralizing the positive donor states.     

漂移层经碳处理后的4H-SiC PiN 二极管的特性与分析

The characteristics of 4H-SiC PiN diodes with a carbon-implanted drift layer was investigated and the reason of characteristics improvement was analyzed. The forward voltage drops of the diodes with carbonimplanted drift layer were around 3.3 V, which is lower than that of devices without carbon implantation, the specific-on resistance was decreased from 9.35 to 4.38 mΩcm² at 100 A/cm², and the reverse leakage current was also decreased. The influence of carbon incorporation in the Si C crystalline grids was studied by using deep-level transient spectroscopy（DLTS）. The DLTS spectra revealed that the Z_1/2 traps, which were regarded as the main lifetime limiting defects, were dramatically reduced. It is proposed that the reduction of Z_1/2 traps can achieve longer carrier lifetime in the drift layer, which is beneficial to the performance of bipolar devices.     

A review of the etched terminal structure of a 4H-SiC PiN diode

The comparison of domestic and foreign studies has been utilized to extensively employ junction termination extension (JTE) structures for power devices. However, achieving a gradual doping concentration change in the lateral direction is difficult for SiC devices since the diffusion constants of the implanted aluminum ions in SiC are much less than silicon. Many previously reported studies adopted many new structures to solve this problem. Additionally, the JTE structure is strongly sensitive to the ion implantation dose. Thus, GA-JTE, double-zone etched JTE structures, and SM-JTE with modulation spacing were reported to overcome the above shortcomings of the JTE structure and effectively increase the breakdown voltage. They provided a theoretical basis for fabricating terminal structures of 4H-SiC PiN diodes. This paper summarized the effects of different terminal structures on the electrical properties of SiC devices at home and abroad. Presently, the continuous development and breakthrough of terminal technology have significantly improved the breakdown voltage and terminal efficiency of 4H-SiC PiN power diodes.     

Defect Analysis of Barrier Height Inhomogeneity in Titanium 4H-SiC Schottky Barrier Diodes

Over 350 4H-SiC Schottky barrier diodes (SBDs) of varying size are characterized using current–voltage (I–V) measurements, with some also measured as a function of temperature. Devices display either a characteristic single-barrier height or atypical dual-barrier heights. Device yields are shown to decrease as device area increases. Molten KOH etching is used to highlight defects for analysis by optical microscopy and atomic force microscopy. The I–V characteristics are compared against the defect density. A positive correlation between effective barrier height and effective electrically active area of the SBDs is found. No correlation is found between threading dislocations and ideality factor or barrier height.     

Influence of operation conditions on true-static DC characteristics and on electro-thermal transient states in silicon carbide Merged PiN Schottky diodes.

In this paper, measured and calculated non-isothermal DC characteristics of silicon carbide MPS devices are investigated, with special attention paid on critical parameters, such as maximum current and junction temperature at which a thermal runaway may occur. Electro-thermal transient states in single MPS devices (forward surge current tests) and in the simple Greatz rectifier are simulated and compared to measurements. Various electro-thermal models of SiC SBDs, with a simplified, effective procedure for calculations of junction temperature are proposed.     

Experimental characterization and numerical analysis of the 4H-SiC p-i-n diodes static and transient behaviour

Steady-state and turn-off switching characteristics of aluminium-implanted 4H-SiC p-i-n diodes designed for high-current density operation, are investigated experimentally and by mean of numerical simulations in the 298-523 K temperature range. The diodes present circular structure with a diameter of 350 μm and employ an anode region with an aluminium depth profile peaking at 6×10¹⁹ cm⁻³ at the surface. The profile edge and the junction depth are located at 0.2 and 1.35 μm, respectively. At room temperature the measured forward current density is close to 370 A/cm² at 5 V with an ideality factor always less than 2 before high-current injection or device-series resistance became dominant. The transient analysis reveals a strong potential of this diodes for use in high-speed, high-power applications, especially at high temperature, with a very low turn-off recovery time (<80 ns) in the whole range of test conditions. The simulated results match the experimental data, showing that the switching performance is mainly due to the poor minority charge carrier lifetime estimated to be 15 ns for these implanted devices.     

Ti/4H-SiC SBD中子辐照效应的研究

采用1 MeV的中子对Ti/4H-SiC肖特基势垒二极管(SBD)的辐照效应进行研究,观察了常温下的退火效应.实验的最高中子剂量为1×1015 n/cm2,对应的γ射线累积总剂量为33 kGy (Si).经过1×1014 n/cm2的辐照后,Ti/SiC肖特基接触没有明显退化;剂量达到2.5×1014 n/cm2后,观察到势垒高度下降;剂量达到1×1015 n/cm2后,势垒高度从1.00 eV下降为0.93eV;经过常温下19 h的退火后,势垒高度有所恢复,表明肖特基接触的辐照损伤主要是由电离效应造成的.辐照后,器件的理想因子较辐照前有所上升;器件的正向电流(VF=2V)随着辐照剂量的上升而下降.     

High doped MBE Si p–n and n–n heterojunction diodes on 4H-SiC

The physical and electrical properties of heavily doped silicon (5×10¹⁹ cm⁻³) deposited by molecular beam epitaxy (MBE) on 4H-SiC are investigated in this paper. Silicon layers on silicon carbide have a broad number of potential applications including device fabrication or passivation when oxidised. In particular, Si/SiC contacts present several atractive material advantages for the semiconductor industry and especially for SiC processing procedures for avoiding stages such as high temperature contact annealing or SiC etching. Si films of 100 nm thickness have been grown using a MBE system after different cleaning procedures on n-type (0 0 0 1) Si face 8° off 4H-SiC substrates. Isotype (n–n) and an-isotype (p–n) devices were fabricated at both 500 and 900 °C using antimonium (Sb) or boron (B), respectively. X-ray diffraction analysis (XRD) and scanning electronic mircorscope (SEM) have been used to investigate the crystal composition and morphology of the deposited layers. The electrical mesurements were performed to determine the rectifiying contact characteristics and band offsets.     

The influence of high energy electron irradiation on the Schottky barrier height and the Richardson constant of Ni/4H-SiC Schottky diodes

The influence of high energy electron (HEE) irradiation from a Sr-90 radio-nuclide on n-type Ni/4H–SiC samples of doping density 7.1×10¹⁵ cm⁻³ has been investigated over the temperature range 40–300 K. Current–voltage (I–V), capacitance–voltage (C–V) and deep level transient spectroscopy (DLTS) were used to characterize the devices before and after irradiation at a fluence of 6×10¹⁴ electrons-cm⁻². For both devices, the I–V characteristics were well described by thermionic emission (TE) in the temperature range 120–300 K, but deviated from TE theory at temperature below 120 K. The current flowing through the interface at a bias of 2.0 V from pure thermionic emission to thermionic field emission within the depletion region with the free carrier concentrations of the devices decreased from 7.8×10¹⁵ to 6.8×10¹⁵ cm⁻³ after HEE irradiation. The modified Richardson constants were determined from the Gaussian distribution of the barrier height across the contact and found to be 133 and 163 A cm⁻² K⁻² for as-deposited and irradiated diodes, respectively. Three new defects with energies 0.22, 0.40 and 0.71 eV appeared after HEE irradiation. Richardson constants were significantly less than the theoretical value which was ascribed to a small active device area.     

Nucleation, growth and retrogrowth of oxidation induced stacking faults in thin silicon-on-insulator

The nucleation, growth, and retrogrowth of stacking faults were investigated for thermally oxidized silicon-on-insulator substrates formed by the separation by implanted oxygen (SIMOX) method. It has been observed that for high oxidation temperatures (T >1150°C) oxidation induced stacking faults (OISFs) undergo a retrogrowth (shrinkage) process at noticeably lower temperatures than in bulk silicon. The retrogrowth process in thin film SIMOX substrates starts at approximately 1190°C for the 2 h thermal oxidations. In this paper, a model for the retrogrowth process is proposed based on the assumption that at high oxidation temperatures vacancies may be injected from the thermal oxide/top silicon interface. We suggest that the vacancy injection reduces the self-interstitial supersaturation and as a direct consequence, attenuates the OISF growth. We also propose that the self-interstitial supersaturation is reduced through point defect recombination inside the silicon overlayer and at the top-silicon/buried-oxide interface where a high density of steps and kink sites are found.