Gate-drain avalanche breakdown in GaAs power MESFET's

The voltage breakdown behavior of a number of different MESFET structures has been investigated using a two-dimensional numerical model. The site of the avalanche is found to be under the drain edge of the gate in recessed devices under all bias conditions, but moves towards the drain contact in planar structures when the channel is not pinched off. The dependence of the breakdown voltage on a variety of geometrical and physical variables has been studied. In particular the surface is shown to play an important part in determining the breakdown voltage.     

Reverse breakdown in GaAs MESFET's

A simple numerical technique for calculating reverse breakdown voltage in GaAs MESFET's is described. The breakdown voltage is determined from an integral over the ionization rate and requires only a small amount of computing time, allowing a variety of structures to be studied. The effects of a gate recess and n⁺layer, the surface potential, buried channel layers, and AlGaAs spacer layers underneath the gate are investigated.     

Surface potential effect on gate—Drain avalanche breakdown in GaAs MESFET's

The surface potential effect on gate-drain avalanche breakdown in GaAs MESFET's is investigated with a two-dimensional device simulator. It is shown that the surface potential effect changes the potential distribution in GaAs MESFET's drastically and therefore plays an important role in determining drain breakdown voltage. In addition, two device structures producing high breakdown voltages, an offset gate structure and a recessed gate structure, are analyzed.     

Power-limiting breakdown effects in GaAs MESFET's

State-of-the-art GaAs MESFET'S exhibit an output power saturation as the input power is increased. Experiments indicated that this power saturation is due to the combined effects of forward gate conduction and reverse gate-to-drain breakdown. This reverse breakdown was studied in detail by performing two-dimensional numerical simulations of planar and recessed-gate FET's. These simulations demonstrated that the breakdown occurs at the drain-side edge of the gate. The results of the numerical simulations suggested a model of the depletion layer configuration which could be solved analytically. This model demonstrated that the breakdown voltage was inversely proportional to the product of the doping level and the active layer thickness.     

Control of gate—Drain avalanche in GaAs MESFET's

The onset of gate-drain avalanche imposes an important fundamental constraint on the drain voltage swing, and hence, on the output power of GaAs FET's. In this paper we show that recognition of the role of surface depletion and proper attention to channel design can yield avalanche voltage factors of 2-3 above bulk values. The appropriate design strategy is minimization of the undepleted epitaxial charge per unit area (Qu) between gate and drain, which, in turn, dictates a gate-notch depth approximately equal to the surface zero-bias depletion depth. A simple lateral spreading model is proposed which predicts thatV_{L} sim 50Qmin{u}max{-1}, where VLis the gate-drain avalanche voltage and Quis measured in units of 10¹²electrons/cm². This prediction is supported by a large body of experimental dc and pulse data, although considerable scatter is observed which we have attributed to epi charge nonuniformities, premature avalanche at the rough edges of AI gates formed by a liftoff process, and surface charging variations associated with dielectric passivation. The observed dependence of VLon epi charge rather than on doping level, as predicted for bulk avalanche, provides convincing evidence for nonbulk two-dimensional avalanche in the thin-film (Q_{u} < 2.3) FET geometry. In thick films (Q_{u} > 2.6), on the other hand, it is found that the bulk avalanche predictions are reasonably accurate. In terms of saturated epi current Is, the bulk regime corresponds toI_{s} > 450mA/mm and the lateral spreading (thin-film) regime toI_{s} < 400mA/mm. Finally, we have found that gate-drain avalanche is the major cause of output saturation as a function of drain potential in power GaAs FET's.     

Accurate modeling for drain breakdown current of GaAs MESFET's

Extensive measurements of a drain breakdown current as a function of device bias are reported in this paper. To represent the measured drain breakdown currents accurately, a new modeling function and an equivalent circuit controlled by two voltages are proposed. This model, when integrated into a large-signal analysis program, improves the accuracy of the simulation     

Numerical analysis of the photoeffects in GaAs MESFET's

The photoeffects on the I-V characteristics of GaAs MESFETs have been studied by a two-dimensional numerical method. It is theoretically verified that the photovoltaic effect occurring at the channel/substrate interface is responsible for the substantial increase of the drain current. The reverse gate current due to illumination is caused by sweep-out by the high electrical field in the gate depletion region, where a large gradient in the depth profile of the hole Fermi energy is found. For devices with a lightly doped n-type buffer layer, the increase of the drain current is less than for devices without a buffer layer, but is still substantial     

Numerical analysis of the looping effect in GaAs MESFET's

The looping effect in the I_D-V_D (drain-current-drain-voltage) characteristics of GaAs MESFETs on semi-insulating substrates has been studied using a two-dimensional numerical analysis. Both the transient and the steady-state behaviors of the looping phenomenon were simulated. Peak voltage- and frequency-dependent behaviors of the looping effect are analyzed. The I_D-V_D loop is due to the difference in the distribution of ionized EL2 concentration when the drain voltage rises and falls because of the trapping process of EL2s. The output conductance is also found to be frequency-dependent and is explained by the frequency-dependent modulation of the potential barrier height at the channel/substrate interface due to the drain-voltage variation     

Backgating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr²⁺and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backgating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Backdating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr/sup 2+/ and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backdating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Floating gates for avalanche suppression in MESFET's

A metal-semiconductor field-effect transistor (MESFET) structure is proposed. It employs one or more uncontacted gate elements between the normal gate and the drain which float in potential in a manner similar to guard rings. These floating gates clamp the maximum electric field at the normal gate and inhibit avalanche breakdown. Numerical modeling of a typical GaAs MESFET with two floating gates demonstrates the field-clamping effect and shows a substantial increase in avalanche breakdown voltage and maximum output power relative to a similar conventional device     

Beyond-punchthrough current in GaAs MESFET's

In a recent letter published in this journal, Patrick et al. reported on a maximum drain voltage for pinchoff Which varied exponentially with gate length in very short-gate GaAs MESFET's. The I-V characteristics given showed that this variation is associated with beyond-punchthrough drain current. Current flowing across a depleted region is an instance of the triode mode of FET operation described by other researchers in 1966. Triode-mode theory can help in the understanding of the behavior of GaAs MESFET's near pinchoff, including the devices of Patrick et al.     

Improvement of the drain breakdown voltage of GaAs power MESFET's by a simple recess structure

Dependence of the drain-to-source breakdown voltage on the drain structure of GaAs power FET's was investigated. It was found that the drain breakdown voltage is improved by a simple recess structure without surface n⁺contact layer. This is due to relaxation of the field at the drain region by increase of the thickness of the active epitaxial layer. The GaAs MESFET with this simple recess structure could be operated up to 24 V. There was no explicit difference in the microwave properties of both recess structure devices with and without the n⁺contact layer. As a practical device, an output power of more than 3 W with 4-dB gain is obtained at 6.5 GHz from this simple recess and cross-over structure GaAs FET.     

Substrate current in GaAs MESFET's

It is shown that the substrate current in GaAs MESFET's may be related to the electron injection into the substrate region adjacent to the high-field domain in the active layer. A simple one-dimensional calculation shows that the substrate current Isubis proportional toVmin{ds}max{1/2}andnmin{0}max{1/4}where Vdsis the drain-to-source voltage, n0is the doping density in the active layer. Atn_{0} = 10^{17}cm^-3andV_{ds} simeq 10V we estimateI_{sub} sim 50mA per millimeter gate in good agreement with experimental results.     

A numerical analysis of avalanche breakdown in short-channel MOSFETs

Recently, the electrical characteristics for the short channel MOSFETs (Metal-Oxide-Semiconductor field effect transistor) have become important because of the increasing density of LSIs (Large Scale Integrated Circuits). One of the methods to understand the characteristics of the short channel MOSFETs is the two-dimensional analysis of the MOSFETs, and many studies about threshold voltage and other items have been made by using the two-dimensional method. In this paper, the drain breakdown characteristics for the short channel MOSFETs are calculated by the two-dimensional analysis method. Consequently, one of the phenomena for the short channel MOSFETs, that the breakdown voltage decreases with increase in gate voltage, is reduced to the difference of the electric field strength distribution from that of the long channel MOSFETs. This variation of the electric field distribution is caused by the strong influence of the electric field from the drain upon the considerable region in the substrate of the short channel MOSFETs.     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

Reliability Study of GaAs MESFET's

Failure modes have been studied phenomenologically on a small-signal GaAs MESFET with a 1mu m aluminum gate. Three major failure modes have been revealed, i.e., gradual degradation due to source and drain contact degradation, catastrophic damage due to surge pulse, and instability or reversible drift of electrical characteristics during operation. To confirm the product quality and to assure the device reliability, a quality assurance program has been designed and incorporated in a production line. A cost-effective lifetime prediction method is presented that utilizes correlations between RF parameters and dc parameters calculated using an equivalent circuit model. Mean time to failure (MTTF) value of over 10/sup 8/ h has been obtained for the GaAs MESFET for an operating channel temperature of 100/spl deg/C.     

Optical Control of GaAs MESFET's

Theoretical and experimental work for the performance of GaAs MESFET's under illumination from light of photon energy greater than the bandgap of the semiconductor is described. A simple model to estimate the effects of light on the dc and RF properties of MESFET'S is presented. Photoconductive and photovoltaic effects in the active channel and substrate are considered to predict the change in the dc equivalent circuit parameters of the FET, and from these the new Y- and S-parameters under illumination are calculated. Comparisons with the measured S-parameter's without and under illumination show very close agreement. Optical techniques can he used to control the gain of an FET amplifier and the frequency of an FET oscillator. Experimental results are presented showing that the gain of amplifiers can be varied up to around 20 dB and that the frequency of oscillators can be varied (tuning) around 10 percent when the optical absorbed power in the active region of the FET is varied by a few microwatts. When the laser beam is amplitude-modulated to a frequency close to the free-running FET oscillation frequency, optical injection locking can occur. An analytical expression to estimate the locking range is presented. This shows a fair agreement with the experiments. Some suggestions to improve the optical locking range are presented.     

A comparative analysis of GaAs and Si ion-implanted MESFET's

In this work, numerical calculations of device characteristics including theI-Vcharacteristic, small-signal parameters, and cutoff frequency are reported for silicon-implanted MESFET devices. The device dimensions and impurity profile are similar to those of GaAs MESFET's. Although Si MESFET devices have not found practical applications, these calculations provide a good comparison of the intrinsic frequency limits of GaAs and Si. Comparative analysis shows that there are differences in the magnitude of the small-signal parameters and channel current between GaAs and Si MESFET devices with the same geometries and implanted profiles. However, the general variations of small-signal parameters with respect to the drain voltage is similar for both materials. In addition, the calculations show that a 1-µm channel length GaAs MESFET device has a higher cut-off frequency by a factor of 1.8 than a similar Si MESFET. These results indicate that GaAs devices are intrinsically better suited for very high-speed switching devices.