Punchthrough-Voltage Enhancement of AlGaN/GaN HEMTs Using AlGaN Double-Heterojunction Confinement

In this paper, we present an enhancement of punchthrough voltage in AlGaN/GaN high-electron-mobility-transistor devices by increasing the electron confinement in the transistor channel using an AlGaN buffer-layer structure. An optimized electron confinement results in a scaling of punchthrough voltage with device geometry and a significantly reduced subthreshold drain leakage current. These beneficial properties are pronounced even further if gate-recess technology is applied for device fabrication. Physical-based device simulations give insight in the respective electronic mechanisms.      

A 0.15-μm 60-GHz high-power composite channel GaInAs/InP HEMTwith low gate current

This letter presents recent improvements and experimental results provided by GaInAs/InP composite channel high electron mobility transistors (HEMT). The devices exhibit good dc and rf performance. The 0.15-μm gate length devices have saturation current density of 750 mA/mm at V_GS=+0 V. The Schottky characteristic is a typical reverse gate-to-drain breakdown voltage of -8 V. Gate current issued from impact ionization has been studied in these devices, in the first instance, versus drain extension. At 60 GHz, an output power of 385 mW/mm has been obtained in such a device with a 5.3 dB linear gain and 41% drain efficiency which constitutes the state-of-the-art. These results studied are the first reported for a composite channel Al_0.65In_0.35As/Ga_0.47In_0.53 As/InP HEMT on an InP substrate     

High-performance InGaP/InxGa1-xAs HEMT withan inverted delta-doped V-shaped channel structure

This letter reports a new and high-performance InGaP/In_xGa_1-xAs high electron mobility transistor (HEMT) with an inverted delta-doped V-shaped channel. Due to the presence of V-shaped inverted delta-doped InGaP/In_xGa_1-x As structure, good carrier confinement and a flat and wide transconductance operation regime are expected. Experimentally, the fabricated device (1×100 μm²) shows a high gate-to-drain breakdown voltage of 30 V and a high output drain saturation current density of 826 mA/mm at V_GS=2.5 V. The high transconductance expands over a very broad operation range with the maximum value of 201 mS/mm at 300 K. Meanwhile, the studied device exhibits a good microwave frequency linearity     

Impact ionization and transport in the InAlAs/n+-InPHFET

We have carried out an experimental study exploring both impact ionization and electron transport in InAlAs/n⁺-InP HFET's. Our devices show no signature of impact ionization in the gate current, which remains below 17 μA/mm under typical bias conditions for L_g=0.8 μm devices (60 times lower than for InAlAs/InGaAs HEMT's). The lack of impact ionization results in a drain-source breakdown voltage (BV_DS) that increases as the device is turned on, displaying an off-state value of 10 V. Additionally, we find that the channel electron velocity approaches the InP saturation velocity of about 10⁷ cm/s (in devices with L_g<1.6 μm) rather than reaching the material's peak velocity. We attribute this to the impact of channel doping both on the steady-state peak velocity and on the conditions necessary for velocity overshoot to take place. Our findings suggest that the InP-channel HFET benefits from channel electrons which remain cold even at large V_GS and V_DS making the device well-suited to power applications demanding small I_G, low g_d, and high BV_DS     

Ga0.51In0.49P/In0.15Ga0.85As/GaAs pseudomorphic doped-channel FET with high-current densityand high-breakdown voltage

Ga_0.51In_0.49P/In_0.15Ga_0.85 As/GaAs pseudomorphic doped-channel FETs exhibiting excellent DC and microwave characteristics were successfully fabricated. A high peak transconductance of 350 mS/mm, a high gate-drain breakdown voltage of 31 V and a high maximum current density (575 mA/mm) were achieved. These results demonstrate that high transconductance and high breakdown voltage could be attained by using In_0.15Ga_0.85As and Ga_0.51In_0.49P as the channel and insulator materials, respectively. We also measured a high-current gain cut-off frequency f_t of 23.3 GHz and a high maximum oscillation frequency f_max of 50.8 GHz for a 1-μm gate length device at 300 K. RF values where higher than those of other works of InGaAs channel pseudomorphic doped-channel FETs (DCFETs), high electron mobility transistors (HEMTs), and heterostructure FETs (HFETs) with the same gate length and were mainly attributed to higher transconductance due to higher mobility, while the DC values were comparable with the other works. The above results suggested that Ga_0.51In_0.49P/In_0.15Ga_0.85 As/GaAs doped channel FET's were were very suitable for microwave high power device application     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

High-breakdown AlGaAs/InGaAs/GaAs PHEMT with tellurium doping

The authors report the fabrication and characterisation of an Al _0.43Ga_0.57As/In_0.2Ga_0.8 As/GaAs pseudomorphic HEMT (PHEMT) with high channel conductivity grown by solid source MBE. The high conductivity of the channel is a direct consequence of the high sheet charge and high mobility that has recently been obtained by using tellurium as the n-type dopant in 43% AlGaAs. The device characteristics reflect the resulting reduction in the parasitic resistances of the high channel conductivity. Microwave measurements yield a short-circuit current gain cutoff frequency f_T of 11 GHz and maximum oscillation frequency f_max of 25 GHz. A high gate-drain breakdown voltage of 26 V along with a maximum drain current density of 400 mA/mm obtained in the device illustrate the applicability of this technology in microwave power field effect transistors     

Optimum design of triode-like JFET's by two-dimensional computer simulation

Design criteria of triode-like JFET's are studied by fully utilizing two-dimensional numerical analysis. The current is caused by tlie carriers injected over a potential barrier in a depleted channel. In contrast to normal pentode-like FET'S, the drain field plays an important role reducing the barrier height and thus causing triode-likeI-Vcharacteristics. Triode-like characteristics depend strongly on device geometry. This operation can be realized only in short gate devices. The channel thicknessais an essential parameter in determining the operational mode. The devices operate as triodes or pentodes corresponding to thin or thick channels, respectively. If applied to low-resistance load direct-drive circuits, the mixed characteristics situated between the triode- and pentode-like ones, are more desirable when compared to pure triode-like ones, This is because of their low on-resistance and high ac power efficiency. The gate-drain distance lgdis also essential in determining breakdown voltage. The design criteria are discussed and an optimum design specified on the ND(channel doping)-aandN_{D} - l_{gd}planes with respect to triode-like characteristics, circuit application and breakdown phenomena. Calculated results are compared with experiments and good agreement is found without using any adjustable parameters. The present design criteria will be useful for designing triode-like JFET's.     

Nitride based high power devices: design and fabrication issues

We have modeled the breakdown voltage, critical current density and maximum operating frequency of several nitride based high power and high temperature electronic devices. It is found that the minority carrier recombination lifetime and the critical field for electric breakdown are important model parameters which influence device design and performance. Planar geometry GaN Schottky devices were fabricated and used to experimentally estimate these important parameters. Current–voltage measurements have indicated the importance of the non-planar geometries for achieving large breakdown voltages. The minority carrier (hole) diffusion length and recombination lifetime have been measured using the electron beam induced current technique. The measured hole lifetime of 7 ns and estimate for the critical field indicate the possibility of AlGaN based thyristor switch devices operating at 5 kV with current densities up to 200 A/cm² and at frequency above 2 MHz. The GaN structural and optical material quality as well as processing requirements for etching are also discussed.     

Experimental characterization of most''s scaled down to the 1 μm level

Fundamental MOS device performances are experimentally analyzed for the projected three levels of scaled-down, silicon-gate devices envisioned in the next decade. The final third-level device having 20 nm thick gate oxide and 0.7 μm effective channel length will have vertical dimension only 0.35 times that of the present 3 μm lithography level. Principal device characteristics discussed are threshold voltage, source to drain breakdown voltage, and effective carrier mobility under practical applied voltage conditions, mainly for dynamic MOS memory operation.

It is found that breakdown voltage reduction is the main obstacle hindering down-scaling, and also that the mobility lowering in the shorter channel length region reduces the merits of down-scaling. MOS device performances for the coming 1 μm geometry level LSI's under practical operation conditions are discussed on the basis of the experimental results obtained.     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

Dependence of hot-carrier immunity on channel length and channelwidth in MOSFETs with N2O-grown gate oxides

The authors report on the channel length (0.5-5 μm) and width (0.6-10 μm) dependence of hot-carrier immunity in n-MOSFETs with N ₂O-grown gate oxides (~85 Å). While channel hot-carrier-induced degradation has a strong dependence on channel geometry in control devices, the degradation and its channel geometric dependences are greatly suppressed in devices with N₂O-gate oxides. Under Fowler-Nordheim injection stress, the control device shows an enhanced degradation with decreasing channel length and increasing channel width, whereas N₂O device exhibits a less dependence on channel geometry     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

Second breakdown and damage in junction devices

Second breakdown has been studied in silicon-on-sapphire (SOS) thin-film diodes using the stroboscopic technique of Sunshine. Nucleation of current filaments, filament growth, and damage through the formation of melt channels are observed and related to the voltage waveforms, geometry, and base layer resistivity. The delay time and the minimum energy for the onset of second breakdown are related to heating of the high-resistivity side of the junction. Theoretical models are presented to describe nucleation of current channels in the junction and the melt transition. A junction channel forms when the sum of minority carrier and thermally generated current densities becomes equal to the local applied current density. The voltage across the junction then goes close to zero locally, but the internal field is not "washed out." The channel is ballasted by the spreading resistance of the high-resistance region. The melt transition is described in terms of a single heat-transfer coefficient characteristic of the device type. As the melt filament grows, the voltage across the filament (and the device) falls. The threshold current for filamentation varies as (ρ^-3/4), where ρ is the resistivity of the high-resistance region. Data on transistors are presented in support of the theoretical models.     

Physical and materials limitations on burnout voltage of GaAs power MESFET's

This paper presents a study of factors limiting the burnout voltage of GaAs power MESFET's. A new device geometry had been investigated. Novel techniques using electron-beam induced current (EBIC) in the drain loop in a scanning electron microscope (SEM) and the shift in carbon Auger line in a scanning Auger microscope (SAM) have been applied to study the bulk electric field distribution and the surface voltage distribution. These techniques have been used to identify the regions of high electric field that lead to device burnout. The highest burnout voltages were observed at 8 × 10¹⁶-cm^-3doping with at least 60-V burnout at full channel current and 85 V near pinchoff conditions. This is a new state of the art. An optimum undoped buffer-layer thickness is observed to be compatible with high burnout voltage and low leakage current. Finally, under optimized conditions of doping and geometry, no improvement is observed in the burnout voltage with the use of a higher doped contact layer.     

The origin of channel currents associated with P+regions in silicon

The mechanism by which very large channel currents can result in P⁺N junctions or in PNP transistors having annular P⁺diffused channel-stop regions was studied in detail using experimental structures whose oxides were intentionally contaminated with sodium ions. It is shown that the onset of channel current flow corresponds quantitatively to the formation of an inversion layer over the P⁺region. Possible mechanisms by which carriers can be supplied to the inversion layer, thereby resulting in a channel current, are considered. It is demonstrated that the mechanism involves the breakdown of the field-induced junction formed between the inversion layer and the underlying P⁺region. The breakdown characteristics of this field-induced junction are considered experimentally in detail. It is shown that breakdown can proceed through either a tunneling or an avalanche mechanism depending on the surface concentration of the P⁺region, and that the breakdown characteristics of field-induced junctions are much like those of narrow alloyed silicon junctions studied earlier by Chynoweth et al.     

Investigation of temperature-dependent characteristics of ann+-InGaAs/n-GaAs composite doped channel HFET

The temperature-dependent characteristics of an n⁺-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor (HFET) have been studied. Due to the reduction of leakage current and good carrier confinement in the n ⁺-InGaAs/n-GaAs CDC structure, the degradation of device performances with increasing the temperature is insignificant. Experimentally, for a 1×100 μm² device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of 24.4 (18.7) V, transconductance of 161 (138) mS/mm, output conductance of 0.60 (0.60) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. The shift of V_th from 300 to 450 K is only 13 mV. In addition, the studied device also shows good microwave performances with flat and. wide operation regime     

A triple channel HEMT on InP (Camel HEMT) for large-signalhigh-speed applications

A triple channel HEMT structure grown on InP has been developed (the “Camel” HEMT). Starting from a dual channel (InGaAs/InP) HEMT that utilizes both the high electron mobility of InGaAs and the low impact ionization coefficient of InP, a third InGaAs channel as well as a quaternary carrier supply layer have been introduced to improve the electron transfer and thus the transistor performance. The design of the new transistor structure and its fabrication technology are described. Static and dynamic performances for an 0.8 μm gate length Camel HEMT are presented and compared to standard double channel HEMT transistors that are fabricated with the same geometry and process conditions. The results show that this new structure offers a very good tradeoff between high breakdown voltage and current gain cutoff frequency     

A silicon MOS magnetic field transducer of high sensitivity

A structure has been devised which converts magnetic flux density change to a change in output current. The structure is essentially a P-channel MOST with the drain diffusion split into two halves. A magnetic field normal to the silicon surface deflects device current towards one half-drain. By operating the MOST in the "pinched-off" mode (VDS> VGS-VT) the output impedance is made high, so that large output voltage swings may be obtained. A theoretical study of the voltage and current distributions in the MOST channel has given data on the influence of device geometry on sensitivity. Experimental results indicate a linear relationship between output current and magnetic flux density, and an unexplained nonlinear variation of output with device current. Comparison of experimental results with theory indicates a carrier Hall mobility in the channel of 116 cm²/V.s.     

A physical model of floating body thin film silicon-on-insulatornMOSFET with parasitic bipolar transistor

An analytical model for SOI nMOSFET with a floating body is developed to describe the I_ds-V_ds characteristics. Considering all current components in MOSFET as well as parasitic BJT, this study evaluates body potential, investigates the correlations among many device parameters, and characterizes the various phenomena in floating body: threshold voltage reduction, kink effect, output conductance increment, and breakdown voltage reduction. This study also provides a good physical insight on the role of the parasitic current components in the overall device operation. Our model explains the dependence of the channel length on the I_ds-V_ds characteristics with parasitic BJT current gain. Results obtained from this model are in good agreement with the experimental I_ds-V _ds curves for various bias and geometry conditions