小面积、低能耗的GF（2^m）域ECC模运算VLSI实现

以面积、能耗为优先准则,研究了GF(2m)域椭圆曲线密码(ECC)模运算VLSI的实现.选择GF(2163)上固定多项式基,引入了简单有效的快速模平方算法和改进的模逆算法,利用串行结构分别实现了模乘、模平方与模逆模块.基于UMC 0.25μm 1.8V工艺库的仿真结果表明,提出的串行模乘、快速组合逻辑模平方和快速模逆VLSI实现方式,通过牺牲域多项式灵活性,能够有效地减小面积、降低能耗,适合于资源受限的ECC系统.     

西尔运算的矩阵分析

本文给出了GF(2)-向量和GF(2)-矩阵的定义,讨论了GF(2)-矩阵的某些性质。用GF(2)-矩阵代替Searle运算,且把这种矩阵分析应用于快速逻辑Walsh变换。     

椭圆曲线密码处理器的高效VLSI设计与实现

采用复合武硬件设计方法，通过数学公式推导和电路结构设计，完成了一款GF（2m）域椭圆曲线密码处理器的高效VLSI实现。以低成本为目标，对算术逻辑模块的乘法、约减、平方、求逆，以及控制电路模块都进行了优化设计。按照椭圆曲线密码的不同运算层次，设计了不同层次的控制电路。该处理器综合在中芯国际SMIC0．18μm标准工艺库上．比相关研究的芯片面积节省48％，同时保证了很快的速度。     

一种基于Normal基椭圆曲线密码芯片的设计

文章设计了一款椭圆曲线密码芯片。实现了GF（2^233）域上normal基椭圆曲线数字签名和认证。并支持椭圆曲线参数的用户配置。在VLSI的实现上，提出了一种新的可支持GF（2^233）域和GF（p）域并行运算的normal基椭圆曲线VLSI架构。其架构解决了以往GF（p）CA算迟后于GF（2^233）域运算的问题，从而提高了整个芯片的运算吞吐率。基于SMIC 0．18μm最坏的工艺，综合后关键路径最大时延3．8ns，面积18mm^2；考虑布局布线的影响，芯片的典型的情况下，每秒可实现8000次签名或4500次认证。     

SM2高速双域 Montgomery 模乘的硬件设计

作为由国家密码管理局公布的SM2椭圆曲线公钥密码算法的核心运算,模乘的实现好坏直接决定着整个密码芯片性能的优劣．Montgomery模乘算法是目前最高效也是应用最为广泛的一种模乘算法．本文基于Mont-gomery模乘算法,设计了一种高速,且支持双域（GF（p）素数域和GF（2m ）二进制域）的Montgomery模乘器．提出了新的实现结构,以及一种新型的W allace树乘法单元．通过对模块合理的安排和复用,本设计极大的缩小了时间消耗与硬件需求,节省了大量的资源．实现256位双域模乘仅需0．34μs ．     

基于FPGA技术的GF(2m)域乘法器的研究和设计

椭圆曲线密码体制以其密钥短、安全强度高的优点获得了广泛的重视和应用,而GF(2m)有限域乘法运算是该密码体制最主要的运算.本文研究了基于FPGA芯片的多项式基乘法器的快速设计方法,并给出了面积与速度的比较和分析.     

基于滑动窗口技术的有限域GF(2n)乘法算法

在分析现有有限域GF(2n)乘法算法的基础上,将滑动窗口技术应用到有限域GF(2n)的乘法运算中,提出了一个基于滑动窗口技术的有限域GF(2n)乘法算法,分析和仿真结果表明,与被认为目前最快的有限域GF(2n)乘法算法一固定窗口算法相比,该算法有更好的实现效率.     

基于GF(2~n)的ECC协处理器芯片设计

文章讨论了定义在GaloisField(GF)2有限域上椭圆曲线密码体制(ECC)协处理器芯片的设计。首先在详细分析基于GF(2n)ECC算法的基础上提取了最基本和关键的运算,并提出了通过协处理器来完成关键运算步骤,主处理器完成其它运算的ECC加/解密实现方案。其次,进行了加密协处理器体系结构设计,在综合考虑面积、速度、功耗的基础上选择了全串行方案来实现GF(2n)域上的乘和加运算。然后,讨论了加密协处理器芯片的电路设计和仿真、验证问题。最后讨论了芯片的物理设计并给出了样片的测试结果。     

高性能可扩展公钥密码协处理器研究与设计

 本文提出了一种高效的点乘调度策略和改进的双域高基Montgomery模乘算法,在此基础上设计了一种新型高性能可扩展公钥密码协处理器体系结构,并采用0.18μm 1P6M标准CMOS工艺实现了该协处理器,以支持RSA和ECC等公钥密码算法的计算加速.该协处理器通过扩展片上高速存储器和使用以基数为处理字长的方法,具有良好的可扩展性和较强的灵活性,支持2048位以内任意大数模幂运算以及576位以内双域任意椭圆曲线标量乘法运算.芯片测试结果表明其具有很好的加速性能,完成一次1024位模幂运算仅需197μs、GF(p)域192位标量乘法运算仅需225μs、GF(2^m)域163位标量乘法运算仅需200.7μs.     

基于GF(2m)的ECC中底层运算的快速实现

椭圆曲线密码系统高速实现的关键是点的数乘与加法,实现点的数乘与加法要在基域中做大量的算术运算,其中最耗时的是域元素的乘法。本文给出了一类有限域GF(2m)中乘法的快速实现方法,该方法简单、高效,容易硬件实现。     

同时实现OR及XOR逻辑运算的多功能计算全息光学元件

本文提出了一种在光学上同时实现两图像间的OR及XOR运算的方法,利用计算全息制成了同时进行上述两种基本逻辑运算的光学元件,并给出了实验结果。     

一个基于相关存储的模式识别方法

应用相关的存储技术实现模式识别可缩减存储大小,但由此带来的饱和问题严重影响系统正常工作,为解决此问题,本文在分析现有系统的基础上给出了基于一系列逻辑操作的识别技术.该技术的实质是用一形式化的方法增加输入模式间的线性无关性.通过论证与实例验证,该方法是有效而实用的.     

IC CAD中的图形运算算法与实现

熊猫系统是一个基于全定制ASIC,同时能完成半定制ASIC设计的完整的ICCAD系统。GOA(Geometric Operations and Analysis tool)是其中的完成图形算术、逻辑、拓扑运算的工具及软件库。本文将介绍它的作用及其与其它工具的关系,并详细介绍了其算法及我们在α测试和β测试中针对速度和精度要求所做的改进工作。     

Optimized reversible arithmetic logic units

Arithmetic Logic Unit(ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4(Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.     

On the Logical Computational Complexity Analysis of Turbo Decoding Algorithms for the LTE Standards

Evaluating the computational complexity of decoders is a very important aspect in the area of Error Control Coding. However, most evaluations have been performed based on hardware implementations. In this paper, different decoding algorithms for binary Turbo codes which are used in LTE standards are investigated. Based on the different mathematical operations in the diverse equations, the computational complexity is derived in terms of the number of binary logical operations. This work is important since it demonstrates the computational complexity breakdown at the binary logic level as it is not always evident to have access to hardware implementations for research purposes. Also, in contrast to comparing different Mathematical operations, comparing binary logic operations provides a standard pedestal in view to achieve a fair comparative analysis for computational complexity. The usage of the decoding method with fewer number of binary logical operations significantly reduces the computational complexity which in turn leads to a more energy efficient/power saving implementation. Results demonstrate the variation in computational complexities when using different algorithms for Turbo decoding as well as with the incorporation of Sign Difference Ratio (SDR) and Regression-based extrinsic information scaling and stopping mechanisms. When considering the conventional decoding mechanisms and streams of 16 bits in length, Method 3 uses 0.0065% more operations in total as compared to Method 1. Furthermore, Method 2 uses only 0.0035% of the total logical complexity required with Method 1. These computational complexity analysis at the binary logical level can be further used with other error correcting codes adopted in different communication standards.

     

Breaking public key cryptosystem based on systems of nonlinear equations over finite field

Tsujii et al. (see ibid., vol.23, no.11, p.558-60, 1987) proposed a public key cryptosystem which requires only O(m/sup 2/) bit operations for encryption/decryption and which also realised digital signatures; m here is the block length. The speed advantage over better known systems such as the RSA system (which takes O(m/sup 3/) operations) could have been immensely significant. Unfortunately it is possible to deduce the private key of the Tsujii system from the public key in polynomial time except possibly in a tiny minority of randomly chosen cases.<>     

List decoding of q-ary Reed-Muller codes

The q-ary Reed-Muller (RM) codes RM/sub q/(u,m) of length n=q/sup m/ are a generalization of Reed-Solomon (RS) codes, which use polynomials in m variables to encode messages through functional encoding. Using an idea of reducing the multivariate case to the univariate case, randomized list-decoding algorithms for RM codes were given in and . The algorithm in Sudan et al. (1999) is an improvement of the algorithm in , it is applicable to codes RM/sub q/(u,m) with u相似文献   

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)

Finite field multiplication is one of the most important operations in the finite field arithmetic and the main and determining building block in terms of overall speed and area in public key cryptosystems. In this work, an efficient and high-speed VLSI implementation of the bit-serial, digit-serial and bit-parallel optimal normal basis multipliers with parallel-input serial-output (PISO) and parallel-input parallel-output (PIPO) structures are presented. Two general multipliers, namely, Massey–Omura (MO) and Reyhani Masoleh–Hassan (RMH) are considered as case study for implementation. These multipliers are constructed by using AND, XOR–AND and XOR tree components. In the MO multiplier, to have strong input signals and have a better implementation, the row of AND gates are implemented by using inverter and NOR components. Also the XOR–AND component in the RMH structure is implemented using a new low-cost structure. The XOR tree in both multipliers consists of a high number of logic stages and many inputs; therefore, to optimally decrease the delay and increase the drive ability of the circuit for different loads, the logical effort method is employed as an efficient method for sizing the transistors. The multipliers are first designed for different load capacitances using different structures and different number of stages. Then using the logical effort method and a new proposed 4-input XOR gate structure, the circuits are modified for acquiring minimum delay. Using 0.18 μm CMOS technology, the bit-serial, digit-serial and bit-parallel structures with type-1 and type-2 optimal normal basis are implemented over the finite fields GF(2²²⁶) and GF(2²³³) respectively. The results show that the proposed structures have better delay and area characteristics compared to previous designs.     

非可逆逻辑门的量子可逆实现研究

逻辑关系可用逻辑函数表示,量子逻辑关系是可逆的,引入和定义了量子逻辑函数;通过引入辅助量子位,增添量子输出信号的区分位,完成对非可逆逻辑门的改造,使非可逆逻辑门在量子电路中得到可逆实现,并研究了一些有用的非可逆逻辑门的改造方法,给出可实现的优化后的量子电路。     

Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

Wireless Personal Communications - Arithmetic Logic Units (ALUs) are very important components of the processor, which performs various arithmetic and logical operations such as multiplication,...