In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Sub-20 ps ECL circuits with high-performance super self-alignedselectively grown SiGe base (SSSB) bipolar transistors

This paper describes a high maximum frequency of oscillation f_max self-aligned SiGe-base bipolar transistor technology, based on a self-aligned selective epitaxial growth (SEG) technology including graded Ge profile in an intrinsic base and link-base engineering using a borosilicate glass (BSG) sidewall structure. The transistor is a new self-aligned transistor, which we call a Super Self-aligned Selectively grown SiGe Base (SSSB) bipolar transistor. The 1st step of the annealing (800°C, 10 min) was performed for the diffusion of boron from the BSG film, before the deposition of an emitter polysilicon film. The 2nd step of the annealing (950°C, 10 sec) of emitter drive-in was carried out, which enabled us to obtain sufficient current gain using in-situ phosphorus doped polysilicon as an emitter electrode. Sheet resistance for a link-region more than one order lower than that of the epitaxial intrinsic base was obtained after heat treatment. Base profile (boron and Ge) design, and the 2-step annealing technique have realized cut-off frequency f_T of 51 GHz and f_max of 50 GHz. ECL circuits of 19-psec gate delay have been achieved     

Novel in-situ doped polysilicon emitter process with burieddiffusion source (BDS)

An in-situ doped polysilicon emitter process for very shallow and narrow emitter formation and minimum emitter resistance is presented. An in-situ doped film was imbedded between two undoped poly spacer layers as a buried diffusion source (BDS) to reduce the emitter resistance and to form a high-quality poly/monosilicon interface. Transistors with an emitter area of 0.25 μm×0.25 μm and with nearly ideal I -V characteristics were fabricated. A cutoff frequency of 53 GHz and a minimum ECL gate delay of 26 ps were achieved using BDS poly emitter transistors with an emitter area of 0.35 μm×4.0 μm     

12-ps ECL using low-base-resistance Si bipolar transistor byself-aligned metal/IDP technology

A self-aligned metal/IDP (SMI) technology is proposed to reduce the external base resistance and to enable fabrication of high-speed bipolar transistors. This SMI technology produces a self-aligned base electrode of stacked layers of metal and in situ-doped poly-Si (LDP) with a small thermal budget by selective tungsten CVD. It provides the low base resistance and a shallow link base for the small-collector capacitance and the high-cutoff frequency. The base resistance is reduced to a half that in a transistor having a conventional poly-Si base electrode. A maximum oscillation frequency of 81 GHz and a 12.2-ps gate delay time in an ECL ring oscillator at a voltage swing of 250 mV were achieved by using the SMI technology even with an ion-implanted base     

73-GHz self-aligned SiGe-base bipolar transistors withphosphorus-doped polysilicon emitters

The authors report a thermal-cycle emitter process using phosphorus for the fabrication of self-aligned SiGe-base heterojunction bipolar transistors. The low thermal cycle results in extremely, narrow basewidths and preservation of lightly doped spacers in both the emitter-base and base-collector junctions for improved breakdown. Transistors with 35-nm basewidths were obtained with low emitter-base reverse leakage and a peak cutoff frequency of 73 GHz for an intrinsic base sheet resistance of 16 kΩ/□. Minimum NTL (nonthreshold logic) and ECL (emitter-coupled logic) gate delays of 28 and 34 ps, respectively were obtained with these devices     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f_max, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively     

超高速双层多晶硅发射极晶体管及电路

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究．这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进,主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的L型侧墙形成技术方面,它有效地减小了器件的基区面积．测试结果表明,晶体管有良好的交直流特性．在发射区面积为3μm×8μm时,晶体管的截止频率为6.1GHz．19级环振平均门延迟小于40ps,硅微波静态二分频器的工作频率为3.2GHz．     

A 0.5-μm very-high-speed silicon bipolar devices technologyU-groove-isolated SICOS

A 0.5-μm high-performance silicon bipolar technology is developed and a very-high-speed emitter-coupled-logic (ECL) circuit is demonstrated. Circuits are fabricated with a 0.5-μm SICOS (sidewall base contact structure) technology featuring U-groove isolation, a shallow impurity profile, and reduced base resistance. A U-groove-isolated SICOS structure is realized by the new self-alignment technology using the double polysilicon planarization method. To reduce the extrinsic base resistance, a large-grain base polysilicon is grown from the amorphous silicon layer. A greatly reduced substrate capacitance and small base resistance are obtained. Using these technologies, a minimum ECL gate delay of 27 ps at F_in =1 is realized. A 20-ps ECL gate will be possible in a device having a smaller emitter and the optimal graft base depth     

A selective-epitaxial-growth SiGe-base HBT with SMI electrodesfeaturing 9.3-ps ECL-gate delay

An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes is developed. A 0.5-μm-wide SiGe base self-aligned to the 0.1-μm-wide emitter was selectively grown by using a UHV/CVD system. This self-aligned structure effectively reduces collector capacitance. In SMI technology, a tungsten film is selectively stacked on all poly-Si electrodes (base, emitter, and collector) in a self-aligned manner by using selective deposition without any heat treatment. So this technology does not cause unwanted diffusion of the base dopants and keeps a shallow intrinsic base profile. SMI technology can therefore provide low parasitic resistances and is well-suited to an SiGe-base HBT. A 2-μm-wide BPSG/SiO₂ refilled trench was introduced in order to reduce the substrate capacitance. The low dielectric constant of BPSG/SiO₂ and the wide trench are very effective in reducing the sidewall element of substrate capacitance. This technology makes it possible to obtain ultra-high-speed operation with a 9.3-ps-gate-delay emitter-coupled-logic (ECL) circuit     

Performance potential of silicon bipolar transistors

The performance potential of silicon bipolar transistors is investigated by device simulation. Using a one-dimensional drift-diffusion equation solver, the SPICE parameters of self-aligned transistors are extracted from doping profiles and device geometries. These parameters are used to predict the CML gate delay for different doping profiles. The validity of this extraction procedure is verified by comparison with experimental data. For a double-diffusion type doping profile with a pinch resistance of 15 k Omega / Square Operator , a transit frequency of 56 GHz and a CML gate delay of approximately 15 ps are achievable. With a doping profile including a low-doped emitter region and a high base doping concentration, significant improvements are found: A transit frequency of 81.6 GHz and a pinch resistance of 10 k Omega / Square Operator enable CML gate delay times below 10 ps.<>     

A scaled 0.25-μm bipolar technology using full e-beamlithography

The full leverage offered by electron-beam lithography has been exploited in a scaled 0.25-μm double polysilicon bipolar technology. Devices and circuits were fabricated using e-beam lithography for all mask levels with level-to-level overlays tighter than 0.06 μm. Ion implantation was used to form a sub-100-nm intrinsic base profile, and a novel in-situ doped polysilicon emitter process was used to minimize narrow emitter effects. Transistors with 0.25-μm emitter width have current gains above 80 and cutoff frequencies as high as 40 GHz. A record ECL gate delay of 20.8 ps at 4.82 mW has been measured together with a minimum power-delay product of 47 fJ (42.1 ps at 1.12 mW). These results demonstrate the feasibility and resultant performance leverage of aggressive scaling of conventional bipolar technologies     

Self-aligned AlGaAs/GaAs HBT with low emitter resistance utilizingInGaAs cap layer

A self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) with an InGaAs emitter cap layer that has very low emitter resistance is described. In this structure, a nonalloyed emitter contact allows the emitter and base electrodes to be formed simultaneously and in a self-aligned manner. The reduction of emitter resistance greatly improves the HBT's transconductance and cutoff frequency. In fabricated devices with emitter dimensions of 2 μm×5 μm, a transconductance-per-unit-area of 16 mS/μm² and a cutoff frequency of 80 GHz were achieved. To investigate high-speed performance, a 21-stage ECL ring oscillator was fabricated using these devices. Propagation delay times as low as 5.5 ps/gate were obtained, demonstrating the effectiveness of this structure     

Advanced process device technology for 0.3-μm high-performancebipolar LSIs

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

Electrical characterization of junctions and bipolar transistorsformed with in situ doped low-temperature (800°C) epitaxial silicon

The results of characterization of junctions and bipolar transistors formed with in situ doped low-temperature (800°C) epitaxial silicon are presented. The epitaxial silicon layers were deposited by ultra-low pressure chemical vapor deposition (U-LPCVD) preceded by an in situ Ar sputter clean, which makes possible 800°C fabrication of bipolar transistors. For emitter layer depositions, the U-LPCVD process was plasma enhanced to attain high donor incorporation. Three typical structures of bipolar transistors (A: with epitaxial collector, base, and emitter; B: with epitaxial base and emitter; and C: with epitaxial base) were fabricated and compared in this study. The junction characteristics of the fabricated transistors were also investigated. Functional transistors were obtained for all three structures. Ideality factor of the junctions formed within the epitaxial silicon were near unity (1.01). These results support the claim that the bulk quality of the low-temperature epitaxial silicon is good enough for device application     

A fundamental limitation for bipolar transistor scaling

A microscopic model of minority-carrier diffusion in a heavily doped emitter is proposed. Monte Carlo simulation demonstrates that statistical fluctuation in the base current is one of the fundamental limitations in high-speed applications of scaled bipolar transistors. For the transistor presently investigated, with 5.0-μm² emitter area, 0.1-μm junction depth, 8.5-ps measurement time, and 0.75-V emitter/base bias, the base current deviation is 43%. This sets up the maximum operating frequency for the transistor. More lightly doped emitters (such as for heterojunction bipolar transistors) will relax this limitation, but at a cost of increased contact resistance, especially when poly-emitters are utilized. Increasing the emitter/base bias will also make the base current rate more deterministic, but the other limitations such as power dissipation and contact resistance will become more obvious     

Ultra-low-power and high-speed SiGe base bipolar transistors forwireless telecommunication systems

Ultra-low-power and high-speed SiGe base bipolar transistors that can be used in RF sections of multi-GHz telecommunication systems have been developed. The SiGe base and a poly-Si/SiGe base-contact were formed by selective growth in a self-aligned manner. The transistors have a very small base-collector capacitance (below 1 fF for an emitter area of 0.2×0.7 μm) and exhibit a high maximum oscillation frequency (30-70 GHz) at low current (5-100 μA). The power-delay product of an ECL ring oscillator is only 5.1 fJ/gate for a 250-mV voltage swing. The maximum toggle frequency of a one-eighth static divider is 4.7 GHz at a switching current of 68 μA/FF     

SiGe drift base bipolar transistor with self-aligned selectiveCVD-tungsten electrodes

A new device and process technology is developed for high-speed SiGe epitaxial base transistors. A 60-nm SiGe epitaxial base and the selectively ion-implanted collector (SIC) structure enhance the cutoff frequency to about 40 GHz. Base resistance is minimized to 165 Ω (emitter area: 0.2×3 μm²), and an f_MAX of 37.1 GHz is achieved by employing 0.2-μm EB lithography for the emitter window, selective CVD tungsten for the base electrode and a self-aligned oxide side wall for the emitter-to-base separation. Circuit simulations predict that this device could reduce the ECL gate delay to below 20 ps     

Analysis of highly doped collector transistors by usingtwo-dimensional process/device simulation and its application of ECLcircuits

A report is presented of the results of an investigation of device parameters and collector-to-emitter breakdown voltages of double polysilicon self-aligned transistors with highly doped collectors using a two-dimensional process/device simulation system. Favourable phosphorous-ion implanting condition for a highly doped pedestal collector was found to achieve a high cutoff frequency as well as low AC base resistance and small base-collector capacitance, thereby keeping the minimum collector-to-emitter breakdown voltage of 3 V. The authors also report ECL circuit performance improvements achieved in experiments that realized a minimum ECL gate delay time of 26.3 ps/gate at switching current of 1.64 mA as a result of process optimization. Moreover, a 1/8 static frequency divider T-F/F has been observed to operate up to a maximum frequency of 15.8 GHz