基于SG/Simulink语音端点检测的设计与实现

为了提高语音端点检测硬件电路的实时性,提出了一种基于短时幅度变化的语音端点检测方法。根据该检测方法,使用赛灵思公司的数字处理系统开发工具实现了端点检测硬件电路的设计。设计中采用了查找表和有限状态机等方法弥补了数字处理系统开发工具中元件库不足的缺点,从而简化了硬件设计,提高了设计的速度。通过协同仿真和现场可编程门阵列元件下载验证表明,该方法可以有效地检测出语音信号的起止点,硬件电路的设计满足系统有效性和准确性的要求。     

SoC有限状态机优化验证方法研究

利用图论及数学规划方法分析并解决有限状态机验证路径的选择优化,提出一种在仿真验证方法中对SOC有限状态机验证路径进行优化的方法．在C＊Core提供的验证环境中,对其部分Golden File验证任务的有限状态机进行了优化处理,通过原方案的验证时间的对比,表明了该方法可以使用更短的时间有效解决有限状态机验证问题．     

基于Verilog HDL的MTM总线主模块有限状态机设计

针对MTM总线主模块的设计需求,在分析MTM总线通信协议基础上,给出了MTM总线主控制模块的有限状态机模型;该有限状态机作为主控制模块的核心,主要用于完成控制MTM总线的消息传送顺序;分析了MTM总线结构体系和有限状态机设计的主要方法步骤,通过QUARTUSⅡ开发平台,基于Verilog HDL语言对该有限状态机进行了设计实现与仿真验证;基于该有限状态机的MTM总线主通信模块已经设计实现,并在工程中得到应用,性能稳定。     

基于FPGA的电梯控制器

本文介绍了基于FPGA设计的一种四层电梯控制器,使用有限状态机实现,采用VHDL语言对其进行描述,通过Quartus II 13.0软件及ModelSim软件进行电路的综合与仿真,验证了此电梯控制器设计的正确性。     

一种针对分组密码的抗能量攻击电路设计

为提高分组密码算法电路的抗能量攻击能力,参考掩码技术的思想,基于取反的基本操作提出了反向交错的概念,对反向交错的关键性质进行了证明,以此为依据设计了一种反向交错的电路结构,并通过加入一级寄存器的方式打乱时序对齐,得到了优化的电路结构,通过功耗随机化的方法提升了算法的抗能量攻击能力。最后将该结构应用到AES-128算法电路中并进行了加解密功能、防护功能和运算性能三方面的验证,结果表明本文设计的电路结构能正确进行加解密,且具有较好的防护效果和运算性能。     

抗差分故障攻击的AES密码芯片设计

针对AES的差分故障攻击(DFA)过程,总结出对AES的DFA攻击算法与攻击模型的特点,在此基础上为AES密码芯片设计了一种基于TRC校验的防护电路,并对其抗差分故障攻击的可行性进行了仿真验证。结果表明,该防护电路能够快速准确地检测出导入错误,增强了AES芯片抗DFA攻击的能力。     

消除状态机毛刺策略探讨

有限状态机是数字系统中的重要组成部分。简单分析了有限状态机产生毛刺的原因,重点讨论了消除有限状态机毛刺的三种方案,比较了它们的优劣及其适用的条件,并以ADC0809采样控制过程为例,给出了实现控制功能的Moore型有限状态机方案和状态码直接输出型有限状态机方案的VHDL语言主要源程序,通过开发工具Max+plusII的功能仿真验证了消除毛刺方案的正确性。     

ASM图在时序电路测试生成中的应用研究

随着电路规模的不断扩大,将测试技术向高层次推进,提高测试的效率成为数字系统测试的必然要求.本文研究了基于ASM图的时序电路测试向量生成方法.该方法根据电路的功能描述构造ASM图,然后将其转换为状态图,利用有限状态机的有关知识构造测试向量,最后通过软件仿真和实测验证说明测试向量的正确性.该方法生成的测试向量能体现系统的功能,且具有较高的故障覆盖率.     

一种交替互补的双状态机自恢复方案

针对深亚微米工艺下瞬态故障引发的软错误可能成为芯片失效的重要原因,提出了一种交替互补的双状态机自恢复结构,该结构将原始状态机拆分为两个子状态机,两个子状态机交替工作,互为补充.在其中一个子状态机发生错误时,回卷到另一个子状态机中的正确状态重新执行,从而有效地针对软错误引起的状态翻转进行防护.为验证本方案,对MCNC91标准电路进行了实验.实验结果显示,在面积开销略为增加的情况下,该方案防护了电路中99.64%的软错误,而电路的延迟比其他同类自恢复方案大幅度降低,在性能改进方面有一定优势.     

PCI总线从接口的设计与验证

讨论了一种包括配置空间和I／O空间的从PCI（PCI-slave）接口电路的verilog HDL设计。重点介绍了顶层的系统架构,对其进行了功能分析和结构划分,并详细阐述了各子模块电路的设计和实现。根据PCI总线交易时序,给出使用有限状态机实现接收总线信号控制本地逻辑的方法。针对PCI时序的复杂性,提出了一种新颖实用的PCI系统验证方法,并重点讲述了组建验证平台的方法及其优点。通过编写测试激励程序完成了功能仿真,仿真和验证的结果表明,该接口电路在功能和时序上符合PCI技术规范,达到了预定的目标。     

基于有限状态机的电梯控制系统故障诊断方法

针对电梯控制系统软故障样本获取困难及产生时间短暂的问题,提出一种基于状态机的故障诊断方法。利用电梯控制开关量和电梯运行模拟量作为状态机的状态特征,在电梯正常运行过程中收集各状态并记录状态转换,以此建立电梯控制系统的规范模型;改进基于有限状态机的被动测试错误检测算法,对待诊断的电梯控制系统进行故障检测/诊断;并不断地确认新的故障情况,完善规范模型。实验结果表明,该方法可以及时检测出未知情况,也可以有效地诊断已知故障,对电梯控制系统瞬间出现的软故障有很好的监督作用。     

基于规范的移动Ad Hoc网络分布式入侵检测

移动ad hoc网络是移动节点自组织形成的网络,由于其动态拓扑、无线传输的特点,容易遭受各种网络攻击。传统的网络安全措施,如防火墙、加密、认证等技术,在移动ad hoc网络中难以应用,因此提出一种基于有限状态机分布式合作的入侵检测算法。首先,将整个网络分为子区域,每一区域随机选出簇头担任监视节点,负责本区域的入侵检测。其次,按照DSR路由协议构筑节点正常行为和入侵行为的有限状态机,监视节点收集其邻居节点的行为信息,利用有限状态机分析节点的行为,发现入侵者。本算法不需要事先进行数据训练并能够实时检测入侵行为。最后,通过模拟实验证实了算法的有效性。     

Fault diagnosis architecture for SKINNY family of block ciphers

Cryptographic hardware and software applications are prone to various attacks either from the environments or from the attacker to gain the secret key. Resource-constrained devices use lightweight cryptographic algorithms to achieve a high level of security. It's always a trade-off between efficient resource utilization and level of security. Out of different attacks, in recent years, fault injection attacks is well matured. It becomes imperative to choose the best and efficient fault diagnosis schemes for lightweight cryptography. In this paper, we propose novel Concurrent error detection (CED), i.e., recomputing with inverted operands (REIO) method for SKINNY Family of Block Ciphers to increase the reliability. The proposed fault detection technique for SKINNY round-based pipelined architecture is adapted. The result shows that the throughput overhead of the SKINNY remains within 2.5% variance for the proposed novel fault detection with a pipelined technique, a maximum of 10% area overhead. We have implemented the proposed fault detection scheme using Xilinx FPGA. Best to our knowledge, there is no CED based fault detection technique proposed in the literature for the SKINNY family of block ciphers. The implementation results show that the proposed scheme is more effective and well suited for resource-constrained environments.     

Fault detection and accommodation of a class of nonlinear systems with unknown multiple time-delayed faults

This paper investigates a fault detection and accommodation (FDA) problem of a class of nonlinear time-delay systems in the presence of unknown multiple time-delayed faults. Compared with existing literature, a main contribution of this paper is to design a time-delay independent FDA scheme, namely, the exact information on time delays is not required to implement the proposed FDA scheme. Under the assumption that the magnitude and occurrence time of multiple faults are unknown, we first design a delay-independent fault detection scheme with a detection threshold for time-delay systems and analyze the fault detectability. Then, an approximation-based fault accommodation design activated after the detection of the first fault is presented for compensating multiple faults. The robustness of the fault detection scheme and asymptotic stability of the tracking error are established through Lyapunov stability analysis. A simulation example is used to illustrate the proposed FDA scheme.     

Robust and efficient detection of DDoS attacks for large-scale internet

In recent years, distributed denial of service (DDoS) attacks have become a major security threat to Internet services. How to detect and defend against DDoS attacks is currently a hot topic in both industry and academia. In this paper, we propose a novel framework to robustly and efficiently detect DDoS attacks and identify attack packets. The key idea of our framework is to exploit spatial and temporal correlation of DDoS attack traffic. In this framework, we design a perimeter-based anti-DDoS system, in which traffic is analyzed only at the edge routers of an internet service provider (ISP) network. Our framework is able to detect any source-address-spoofed DDoS attack, no matter whether it is a low-volume attack or a high-volume attack. The novelties of our framework are (1) temporal-correlation based feature extraction and (2) spatial-correlation based detection. With these techniques, our scheme can accurately detect DDoS attacks and identify attack packets without modifying existing IP forwarding mechanisms at routers. Our simulation results show that the proposed framework can detect DDoS attacks even if the volume of attack traffic on each link is extremely small. Especially, for the same false alarm probability, our scheme has a detection probability of 0.97, while the existing scheme has a detection probability of 0.17, which demonstrates the superior performance of our scheme.     

识别密码算法具体实现中潜在功耗攻击的理论分析方法

为验证密码算法具体实现技术抗功耗攻击的有效性,提出一种可发现在密码算法具体实现中可能存在的功耗攻击的分析方法,主要包括识别潜在攻击的基本理论、描述密码算法具体实现的增强数据相关图、根据基本理论和增强数据相关图以识别不同强度功耗攻击的算法,并给出针对一种典型的AES算法防护技术的分析结果.结合文中的结果以及密码算法部件抗功耗攻击能力的量化分析,可以建立相应的抗功耗攻击的设计流程.     

FCT网络的并发错误检测结构

文中提出了一种快速离散余弦变换电路的开发错误检测结构。为了达到１００％的故障覆盖率,ＦＣＴ采用基于第３类离散余弦变换的Ｂ．Ｇ．Ｌｃｅ算法蝶型结构实现。     

一种抗同步攻击的视频水印新方案

文章提出一种新颖的基于纠错和同步编码的视频水印方案,在嵌入水印时先将水印信息进行纠错编码后,和同步码作数据封装,然后嵌入到视频数据中。在检测水印时,先检测同步码,然后对得到的信息码进行纠错译码,还原出水印信息。此外,为了抵抗几何攻击,算法利用Zernike矩来确定水印嵌入的位置。实验表明,该水印方案具有低复杂性,能够有效抵抗帧丢失、帧插入等时间域的同步攻击与几何攻击。     

A high-speed AES design resistant to fault injection attacks

To secure the Advanced Encryption Standard against physical attacks known as fault injection attacks, different countermeasures have been proposed. The AES is used in many embedded systems to provide security. It has become the default choice for security services in numerous applications. However, the natural and malicious injected faults reduce its robustness and may cause private information leakage. In this paper, we study the concurrent fault detection schemes for achieving a reliable AES implementation. We specifically propose a new fault detection scheme based on modification of the AES architecture. For this purpose, the round AES transformation is broken into two parts and a pipeline stage is inserted in between.The proposed scheme is independent of the way the S-Box and the Inv_S-Box are implemented. Hence, it can be used for both the S-Box and the Inv_S-Box using Look-Up Table and those using logic gates based on Galois Fields. Our simulation results show the fault coverage reaches 98.54% for the proposed scheme. Moreover, the proposed and the previously reported fault detection schemes have been implemented on the most recent Xilinx Virtex FPGAs. Their area overhead, the frequency and throughput have been compared and it is shown that the proposed fault detection scheme outperform the previously reported ones.     

一种离散余弦变换电路的并发故障检测结构…

本文提出了一种离散余弦变换 (DCT)电路的并发故障检测结构。DCT采用 B.G.L ee算法蝶型结构实现 ,检测采用的方法是基于算法的并发故障检测容错方法。与其它并发故障检测容错结构相比 ,本文提出的并发故障检测 DCT结构在硬件及时间冗余度上均优越