系统芯片 IDDQ 可测试设计规则和方法

目的：为了使IDDQ测试方法对SOC（系统芯片）IC能继续适用，必须实现SOCIDDQ的可测试性设计，解决因SOC设计的规模增大引起漏电升高的问题。方法：传统的电路分块测试方法存在需要增加引腿代价，因此是不实际的，本文提出了一种通过JTAG边界扫找控制各个内核电源的SOCIDDQ可测试设计方法。结论：实验表明该设计不要求专门的控制引腿，硬件代价是可忽略的，结论：本文提出的方法可有效地用于系统芯片的IDDQ测试。     

基于CygnalC8051F系列SOC电力参数分析仪的设计和实现

文章主要介绍一种基于Cygnal C8051F系列单片机SOC（System on chip集成的混合信号片上系统）的电力参数分析仪硬件设计。该系统由前置电路、零点校准调整电路和主控电路三部分组成，采用数字相移及自动校准技术对抽油机电动机的运行参数及抽油机对电网充电电流的大小进行测试。由于能对电流的相量进行定性分析，能更准确地测量抽油机电流平衡比，为油田管理部门提供了科学的测量数据。     

SOC和串行大容量存储器在随钻测试中的应用

文章阐述了基于80511P核的片上系统（SOC）ADUC812和串行大容量FLASH存储器在石油钻井随钻测试中的应用。该系统可以测试扭矩、钻压、侧向力、环空压力等工程参数。系统主要包括数据采集、数据存储和数据传输三个模块。     

SOC及IP复用技术探讨

随着集成电路按照摩尔定律的发展,芯片设计已经进入了系统级芯片(SOC)阶段,在这里介绍了SOC的概念,尤其介绍关键技术IP核的复用。     

基于SOC技术的三相电力能效监测终端硬件设计

随着智能电网的深入发展,为了满足国网公司对能效监测的要求,设计了一种基于SOC技术的三相电力能效监测终端。它采用锐能微RN8316(SOC)为主控芯片,通过管脚资源配置,实现了电流电压采样计量、直流模拟量采样、电压质量监测、通信等功能。文中介绍了电力能效监测终端的硬件设计,提供了完整的设计方案,该方案不仅能提高终端的稳定性和可靠性,还能降低物料数量和生产成本。     

基于FPGA的高速串行传输技术设计与实现

基于嵌入式系统的板级传输特性，提出一种高速串行解决方案。在FPGASD高速收发器构成的传输模块中，利用SOC（片上系统）的IP核完成3．2Gpbs的全双工通讯。对该方案进行仿真和实际测试，达到了预期的效果。     

安时-卡尔曼交叉运行的电池荷电状态估算策略及其微控制器在环验证

为了提高电池管理系统(BMS)的性能,研究了电池荷电状态(SOC)的估算方法,并根据SOC估算算法精度和系统实时性要求,提出了安时(AH)积分算法-卡尔曼(Kalman)算法(AH-Kalman)交叉运行的SOC估算策略。该策略用开路电压(OCV)法确定SOC初值,以实时性较强的AH积分法为主,采用间歇运行的Kalman滤波法修正安时计量法积分误差。建立了系统仿真模型,验证了卡尔曼滤波算法对安时积分法积累误差的修正作用。将控制算法生成C代码下载到目标控制器,搭建微控制器在环测试验证(PILS)平台,进行了与传统卡尔曼滤波算法的复杂度对比分析。结果表明,所提出AHKalman交叉运行的SOC估算策略在保证了SOC估算精度的同时也具有较好的实时性,便于实际应用。     

基于改进型能量守恒SOC估算法的电动汽车三段式智能充电方式研究

为研究电动汽车安全、快速的智能充电方式,基于传统能量守恒法,考虑电池容量衰减和电池内阻损失对荷电状态(state of charge,SOC)估算的影响,提出改进型能量守恒SOC估算方法。对比分析几种传统充电方式,根据马斯定理确定最佳充电电流,提出以改进型能量守恒SOC估算法得到的SOC值作为判断依据的电动汽车三段式(小电流充电、脉冲充电、恒压充电)智能充电方式,并建立其仿真模型。结果表明:改进型能量守恒SOC估算法得到的SOC值要小于传统能量守恒法,其更加接近真实SOC值;三段式智能充电方式能根据电池组SOC值的变化智能地选择具体充电方式,实现了对电池的安全、快速充电。提出的基于改进型能量守恒SOC估算的三段式智能充电方式对当前电动汽车充电方式的研究提供了一定的参考价值,为智能充电方式研究效能的提升提供了一种可行方法,也为智能充电理论应用于工程实践打下基础。     

基于MSP430单片机的高精度转台角速率校准系统设计

为了对转台进行现场校准,设计了一套基于MSP430单片机的高精度转台角速率校准系统,实现了对速率转台的高准确度角速率测量校准,并给出了测试实例.该系统采用定时测角法,用高准确度恒温温补晶振作为时间基准时钟,用单片机控制正交解码芯片HCTL-2032,对圆光栅传感器输出的正交信号进行解码计数,同时设计了硬件周期同步电路,...     

动力电池测试系统充放电电流校准的研究

动力电池测试系统是检测电池性能的主要设备。针对动力电池测试系统的校准,国内目前还未颁布相关的检定规程和校准规范,研究一种合理、方便、科学的校准方法非常必要。本文简单介绍了动力电池测试系统的计量特性,深入研究了动力电池测试系统充放电电流的校准方法和校准装置的选择,并对校准结果进行不确定度评定。     

论航空装备的测试性与计量及计量性设计

分析了测试与计量的关系及测试设备的计量特性;论述了BITE,ATE等设备的计量需求;以装备研制过程贯彻计量性设计为主线,分析了计量性设计的工作内容及BITE和ATE的计量性设计策略,从理论上为装备测试的可计量提供支持。     

Improved Test Methodology for Production Testing of RF Switches Using a New Relative Measurement Technique

High-volume production testing using automatic test equipment (ATE) is an important part of the integrated circuit manufacturing industry, where it allows products to be rigorously characterized to ensure conformity with their data-sheet specifications. When used in production, the accuracy and repeatability of the ATE must itself be understood so that the final measurements are a true reflection of the underlying product performance and are not adversely influenced by variations or inaccuracies in the ATE setup. This paper reports on the application of the ATE to production testing of CMOS solid-state RF switches operating at 1 GHz and the steps that have been taken to remove sources of variation from the measurement setup. In particular, a calibration path based on the solid-state GaAs switches, which shares most of the RF signal path with the device under test (DUT), is described. The introduction of the calibration path reduces the variability of the measurement system by up to 60%, thus ensuring the suitability of the new setup for an ongoing high-volume production test.     

CAD navigation and diagnostics by linking ATE and EDA

This paper describes a specific methodology and software that links automated test equipment (ATE) and electronic design automation (EDA) tools to identify and diagnose failures at the layout level. The ATE software, named wafer fail layout map (WFLMAP), works in concert with the EDA integrated circuits (IC) design database and provides computer-aided design (CAD) navigation and correlation between the tester failure data and IC design data. With this approach, layout-level defect diagnosis is achieved at the individual chip level, as well as at the wafer level. This method can also be used for improved design for manufacturing (DFM).     

Architecture and design of an open ATE to incubate the development of third-party instruments

To test next-generation system-on-a-chip (SoC) ICs, an open architecture automatic test equipment (ATE) has been conceived. Open architecture provides a framework to integrate software and instruments of different vendors into the ATE. The specifications of this framework, known as OPENSTAR specifications, have been developed by the Semiconductor Test Consortium (STC). The deployment of third-party instruments and modules in this framework is plug-and-play to achieve the optimal test configuration for a given SoC. In this test system, each modular unit can be replaced with another modular unit from a different vendor, and the tester can be reconfigured to map the test resources according to the requirements of device-under-test (DUT). The only restriction in using the third party modules is that each modular unit must adhere to the standard interfaces of the integrating framework and should conform to the OPENSTAR specifications. Hardware modules can be any functional unit such as a digital pincard, an analog card, device power supply (DPS), instruments such as waveform generator, etc. Similarly, software modules can be a tool or utility such as a test executive tool, system monitoring or licensing tools, unit-level controllers, database, microsoft office utilities, application specific software for controlling equipment, etc. The basic structure of this test system, module structure, calibration/diagnostics and synchronization as well as system reconfigurability is described in this paper.     

Analysis and measurement of fault coverage in a combined ATE and BIST environment

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test equipment (ATE), and presents closed-form expressions for fault coverage as a function of the number of BIST and ATE test vectors. This requires incorporating the time to switch from BIST to ATE (referred to as switchover time), and utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment, we model fault coverage as a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed; this approach is initially based on fault simulation using a small set of random vectors; an estimate of the so-called detection profile of the circuit under test is established as the basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE as related testing processes.     

Evaluation, analysis, and enhancement of error resilience for reliable compression of VLSI test data

This paper focuses on error-resilience, the capability of a test data stream [which is transferred from an automatic test equipment (ATE) to the device under test (DUT)] to tolerate errors. These errors may occur in an ATE, either in the electronics components of the loadboard or in the high-speed serial communication links. Initially, it is shown that the combined effect of such errors and test data compression can seriously degrade the test quality (as measured by coverage) of the compressed data streams. The effects of errors on compressed streams are analyzed and various test data compression approaches are evaluated. It is shown that for benchmark circuits, the coverage of test sets can be reduced by 10%-30%. Next, two redundancy-based techniques are proposed to improve error-resilience. The objective of the redundant data is to limit the erroneous effect due to bit-flips once the sequence is decompressed. Through extensive simulation, it is substantiated that for the same benchmark circuits and using different compression techniques, the reduction in coverage is only 0.20%-3.52% for a combination of both redundancy techniques. The impact of redundancy techniques on compression ratio is evaluated by experiments and analysis for various test data compression approaches.     

Higher Reliability for Hybrids and Printed Circuit Boards by Functional Thermal Testing

Thermal cycling of functioning electronic assemblies has proven to be a means to enhance field-reliability. This paper describes a unique testing device which proved to be both practical and cost-effective for performing rapid thermal cycling on automatic test equipment (ATE). By using liquid nitrogen for quick cooling and the resulting inert gas as the media to be blown across electronic assemblies, many gains were made in quick proof-of-design tests. A unique manual switching arrangement from a pair of commercially available chambers provides quick changeover from hot to cold ambient environment around the units under test (UUT). Adding blowers to each chamber for circulating the inert gas across the UUT achieves rapid temperature changes. New MIL specification requirements can now be met and the proven reliability enhancement techniques can now be used with any ATE. A programmed temperature cycle is also part of the features available from the Thermal Test Station (TTS) described.     

Depot ATE Architecture and Instrumentation Considerations

To make effective use of the resources available at large test and diagnostic centers, to reduce costs, and to provide timely and adequate service, automatic test equipment (ATE) must be so designed that it can solve many of the unique problems facing these centers. These problems include: support of many priorgeneration, semiautomatic, and ATE's of varying design; high-throughput requirements and support of a wide variety of units under test (UUT); and need for more automation because of difficulties in obtaining and keeping trained personnel. This paper identifies the limitations in the system architecture of the present uniprocessor, single-station, serially tasked ATE; it then describes several proposed alternatives. These are versatile designs and instrumentation with such features as: large-scale file-handling capability; ability to emulate prior-generation ATE and to support complex compilers and runtime packages; and fast, multiple-station capability with automatic UUT identification and audio-response output for increased operator efficiency.     

Analysis and evaluation of multisite testing for VLSI

This paper deals with multisite testing of VLSI chips in a manufacturing environment. Multisite testing is analyzed and evaluated using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, fault coverage, and touchdown time for the head). The presence of idle time periods and their impact on the multisite test time is analyzed in depth. Two hybrid testing scenarios which combine built-in self-test (BIST) and automatic test equipment (ATE) are proposed and analytical models are provided to establish the corresponding multisite test time. It is shown that a hybrid approach based on screening chips through a BIST stage improves the performance of multisite test and allows a better utilization of channels in the head of an ATE.     

A Programmable Display Test Unit

The present approach to testing and aligning complex avionic information display systems such as those in the F-14A, E-2C, and S-3A aircraft has been highly specialized, and military experience with this approach reveals that it is complicated, time-consuming, and often seriously compromises test effectiveness. Attempts to use general-purpose automatic test equipment (ATE) for display testing also have not been entirely successful because of the need for highly complex, externally situated equipment and adapters. Based on this premise, PRD Electronics has undertaken the development of a unique display test unit which under program control meets the test needs of many display systems, such as those in the A-7E and F-18 aircraft, without proliferation of hardware and without the need for "reengineering" the unit for each new application. Program control provides Electronic Industries Association (EIA) standard video formats as well as various test patterns for performance evaluation. This paper addresses the overall system considerations as well as some of the unique techniques employed.