A 400-MT/s 6.4-GB/s multiprocessor bus interface

This paper describes the design of a system bus interface for the 130-nm Itanium/sup /spl reg//2 processor that operates at 400MT/s (1 megatransfer = 1 Mb/s/pin) with a peak bandwidth of 6.4 GB/s. The high-speed operation is achieved by employing source-synchronous transfer with differential strobes. Short flight time is accomplished by double-sided placement of the processors. Preboost and postboost edge-rate control enables fast clock-to-output timing with tight edge-rate range. The built-in input/output (I/O) loopback test feature enables I/O parameters to be tested on die, using a delay-locked loop and interpolator with 21-ps phase-skew error and 15-ps rms jitter. Power modeling methodology facilitates accurate prediction of system performance.     

132.2-Gb/s PDM-8QAM-OFDM Transmission at 4-b/s/Hz Spectral Efficiency

In this letter, we investigate 132.2-Gb/s polarization- division-multiplexed orthogonal frequency-division-multiplexing (PDM-OFDM) transmission at 25-GHz channel spacing. We show that the nonlinear tolerance is dependent on the OFDM symbol length. By using 14.4-ns-long OFDM symbols, 7 $, times ,$132.2-Gb/s transmission of PDM-OFDM at 4-b/s/Hz spectral efficiency is reported over 1300-km standard single-mode fiber.      

100-Gb/s Packet Signal Generation With Spectral Efficiency Larger Than 1 bit/Hz/s

We have experimentally demonstrated how to generate 100-Gb/s packet signals with spectral efficiency higher than 1bit/Hz/s for the first time. The optical packet with 3.125-Gb/s label and 100-Gb/s return-to-zero differential quadrature phase-shift-keying payload are generated by using optical carrier-suppression and separation and vestigial sideband filtering techniques. The performance of transmission and label erasure has also been evaluated.     

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 2$^{11}-$1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.      

FSK heterodyne transmission experiments at 560 Mbit/s and 1 Gbit/s

Optical frequency-shift-keying (FSK) signals are obtained from directly modulated distributed feedback (DFB) semiconductor lasers. Experimental studies of the direct frequency modulation (FM) characteristics of the DFB lasers show a nonuniform FM response due to the competing effects of thermal modulation of the laser active region and carrier density modulation. Equalization of the signal current to the laser is employed to produce a flat FM response from 30 kHz to 1 GHz. Optical FSK transmission and heterodyne detection experiments at 560-Mbit/s and 1-Gbit/s are conducted at a wavelength of 1497 nm. Receiver sensitivities of -39 dBm at 560 Mbit/s and -37 dBm at 1 Gbit/s are obtained. Transmission through 100 km of single-mode fiber at 1 Gbit/s is achieved with no degradation in receiver sensitivity.     

一种用于14位250 MS/s ADC的3.5 Gb/s发送器

提出了一种用于14位250 MS/s ADC的数据发送器。该发送器输出采用电流模驱动方式,最高数据传输速率达3.5 Gb/s,数据输出仅需要2个数据端口。电路采用180 nm 1.8 V 1P5M CMOS工艺实现。测试结果表明,该发送器在3.5 Gb/s速率下的输出信号摆幅为800 mV,抖动峰峰值为100 ps,功耗为32 mW。采用该3.5 Gb/s数据发送器的ADC在250 MHz采样率下得到的信噪比为71.1 dBFS,无杂散动态范围为77.6 dB。     

Bipolar optical FSK transmission experiments at 150 Mbit/s and 1Gbit/s

Bipolar direct modulation has been used to overcome the nonuniform low-frequency modulation response of distributed-feedback laser transmitter in optical FSK transmission experiments at 150 Mb/s and 1 Gb/s. The heterodyne receiver sensitivity was -48 dBm for 150 Mb/s and -39 dBm for Gb/s, independently of the pseudorandom pattern length. There was no degradation in receiver sensitivity with transmission through more than 100 km of fiber     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.     

基于10 Gb/s传输链路的40 Gb/s光传输实验研究

基于中国自然科学基金网(NSFCNet)的400 km×10 Gb/s光传输链路实现了40 Gb/s光传输,没有出现误码率(BER)平台,说明在常规的中短距离10 Gb/s系统可以直接升级至40 Gb/s系统,而不需要升级传输链路。但是,由于相对10 Gb/s系统而言40 Gb/s系统的色散容限非常小,在升级时必须精确补偿原有链路的色散,在接收机前一般需要加可调色散补偿单元。同时,还分析了光纤注入功率对系统性能的影响,结果表明在设计这种由10 Gb/s向40 Gb/s升级的系统时,不仅要考虑信号带宽增加带来信噪比要求的提高,而且必须充分考虑光纤非线性的影响。     

2.56 Tbit/s (32×80 Gbit/s) polarisation-bit-interleavedtransmission over 120 km NDSF with 0.8 bit/s/Hz spectral efficiency

Experimental results of 32×80 Gbit/s polarisation-bit-interleaved carrier-suppressed RZ transmission over 120 km of NDSF with 0.8 bit/s/Hz spectral efficiency are reported. System Q values between 6.1 and 8 (2³¹-1 pattern) were achieved with the use of distributed Raman amplification and polarisation demultiplexing     

3.2 Tbit/s (80 × 40 Gbit/s) phase-shaped binary transmissionover 3 × 100 km with 0.8 bit/s/Hz efficiency

50 GHz-spaced 80 × 40 Gbit/s WDM transmission over 300 km of TeraLight^TM fibre is demonstrated without polarisation demultiplexing, using the PSBT format. A record capacity of 3.2 Tbit/s is thus achieved over the C-band only, with a spectral efficiency of 0.8 bit/s/Hz     

10 Gsample/s optoelectronic A/D converter

A 5 bit, 10 Gsample/s flash A/D converter (ADC) is fabricated for 10 Gbit/s optical receivers. To achieve a 10 Gsample/s rate with wide signal bandwidth, the design focuses on reducing aperture uncertainty, clock skew, and metastability error. The ADC achieves 4.1 effective bits at low input frequencies and 2.8 effective bits at 4.9 GHz input signal at 10 Gsample/s.     

25 Gbit/s decision circuit, 34 Gbit/s multiplexer, and 40 Gbit/s demultiplexer IC in selective epitaxial Si bipolar technology

A 25 Gbit/s decision circuit, a 34 Gbit/s multiplexer, and a 40 Gbit/s demultiplexer IC have been realised with selective epitaxial silicon bipolar technology using 0.8 mu m lithography. The data rates achieved are the highest values reported for these types of circuit in any IC technology.<>     

10Gbit/s并行光收发模块在万兆以太网的应用

介绍了万兆以太网技术（10 gigabit ethernet technology) . 万兆以太网使用以太网结构实现10Gbit/s点对点传输，距离可达到40km，使以太网的应用从局域网扩展到城域网和广域网. 重点介绍了万兆以太网的功能结构、分层结构、物理传输介质和甚短距离（very short reach）网络传输的并行光传输系统在万兆以太网方面的应用.     

86 Gbit/s SiGe receiver module with high sensitivity for 160/spl times/86 Gbit/s DWDM system

A 86 Gbit/s SiGe receiver chip with an on-chip phase-locked loop and a preamplifier is presented. The chip is mounted and measured in a module assembly with RF-connectors. At the intended system data rate of 86 Gbit/s bit-error-free operation at a high input sensitivity of 50 mV/sub pp/ is demonstrated. With an external clock, high-speed capability is proven by error-free operation up to 100 Gbit/s     

1.52 Tbit/s OCDM/WDM (4 OCDM×19 WDM×20 Gbit/s)transmission experiment

1.52 Tbit/s OCDM/WDM (4 OCDM×19 WDM×20 Gbit/s) transmission based on simultaneous multi-wavelength optical encoding of a single supercontinuum source is experimentally demonstrated with 0.4 bit/s/Hz spectrum efficiency     

A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays

A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-mum CMOS process, is presented. A fast lock time of 7.5 mus and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm² and consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.     

640 Gbit/s (32×20 Gbit/s) WDM transmission with 0.4(bit/s)/Hz spectral efficiency using short-period dispersion-managedfibre

640 Gbit/s (32 channel×20 Gbit/s) WDM transmission with 0.4 (bit/s)/Hz spectral efficiency is demonstrated using short-period dispersion-managed fibre (Perfect Cable^TM). The average Q-factor was measured to be better than 18 dB after transmission over 280 km     

Bandwidth virtualization enables long-haul WDM transport of 40 Gb/s and 100 Gb/s services

This article describes how bandwidth virtualization can enable transmission of ultra-high bandwidth 40 Gb/s and 100 Gb/s services over existing optical transport networks independently of the underlying network infrastructure. An overview of the technology alternatives available to enable high-bandwidth service transport is provided, along with a discussion of the relative merits of different approaches. The authors describe how wavelength division multiplexing, using large- scale photonic integrated circuits combined with the use of a digital virtual concatenation mapping protocol, can be used to enable decoupling of 40 Gb/s and 100 Gb/s service provisioning from the underlying optical link engineering, thereby enabling bandwidth virtualization. Real-world implementation examples of bandwidth virtualization are provided, including 40 Gb/s service transmission over a 2000-km fiber link with 65 ps of peak PMD, a field trial of 40 Gb/s service transmission over an 8477-km trans-oceanic network, and finally a field trial of a pre-standard 100 gigabit Ethernet service transmission over a 4000-km terrestrial long-haul network.     

Parallel-optical interconnects >100 gb/s

A parallel-optical interconnect with 12 channels operating at 8.5 Gb/s giving an aggregate data rate of 102 Gb/s is demonstrated, to the authors' knowledge, for the first time. The paper describes and demonstrates 13 /spl times/ 16-mm cross-section 12-channel parallel-optic transmitter and receiver modules with each channel operating at a data rate of 8.5-10 Gb/s. This was achieved using bottom-emitting 990-nm vertical-cavity surface-emitting lasers and bottom-illuminated InGaAs-InP photodetectors flip-chip bonded directly to 12-channel transmitter and receiver integrated circuits, respectively. In addition, 102-Gb/s link results are demonstrated over 100 m of 50-/spl mu/m-core standard multimode ribbon fiber. A bit-error ratio of <10/sup -13/ was measured on a single channel after transmission through 100 m of multimode fiber at a data rate of 8.5 Gb/s with all 12 channels operating simultaneously.