Hot Chips Turns 20 [Guest editors' introduction]

The five papers in this special issue are extended versions of papers presented at the Hot Chips conference in August 1008.     

Hot Chips 16: Power, Parallelism, and Memory Performance

We are pleased to introduce this special issue of IEEE Micro featuring papers that capture the best presentations from the Hot Chips 16 conference held last summer at Stanford University.     

Guest Editors' Introduction: Hot Chips 19

This special issue showcases articles written from five of the best presentations at the Hot Chips 19 conference, held in August 2007. The guest editors give highlights of the conference and introduce the articles, which cover the mobile-optimized northbridge of AMD's Griffin microprocessor family; the IBM z10 next-generation mainframe microprocessor; fault tolerance in IBM's Power6 microprocessor; NVIDIA's Tesla unified graphics and computing architecture; and SiBEAM's 4-Gbps 1080p-capable uncompressed HD A/V wireless 60-GHz transceiver chipset.     

Thousand-Core Chips [Roundtable]

The 2007 Design Automation Conference (DAC) had a special session entitled "1000 Core Chips," which was organized by Radu Marculescu (Carnegie Mellon University) and Li-Shiuan Peh (Princeton University). This session examined some of the ramifications of multicore chip design from four perspectives: technology, architecture, programming, and design automation. In this roundtable, held immediately following the conference session, the presenters expounded on the future of multicore chips with respect to education, programming languages, operating systems, and design automation.     

Guest Editors' Introduction: Hot Chips 17

Guest Editors John Sell and Alan Jay Smith talk about what went into the presentation of IEEE Micro's Hot Chips 17 issue.     

New Methodologies for Parallel Architecture

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. Computers, etc.     

基于机器视觉的芯片引脚缺陷检测系统设计与实现

针对双球红外接收头芯片人工缺陷检测难度大、误判率高等问题,设计了一个基于机器视觉的引脚缺陷检测系统,对双球红外接收头芯片的引脚进行缺陷检测,达到分辨出合格品和瑕疵品的目的;首先,通过工业相机实时采集芯片图像,并对图像进行滤波、灰度化等预处理;然后利用VisionPro视觉软件的PMAlign工件进行图像特征匹配,计算引脚个数以判断引脚是否缺失,利用AnglePonitPonit工具计算引脚间距以判断引脚是否弯曲;最后将检测到的芯片位置信息和识别结果通过socket通讯协议发送给工业机器人;工业机器人根据识别结果,将合格品和瑕疵品分别抓取至不同区域,实现对芯片的分类管理;实验结果表明,该缺陷检测系统误判率为0.4%,满足工业生产的要求。     

Book Reviews: NoC, NoC ... Who's there?

This is a review of Networks on Chips: Technology and Tools, by Giovanni De Micheli and Luca Benini. This comprehensive survey and integrated reference work on networks on chips (NoCs) offers both breadth in covering most of the major work in this area and depth in delving into all the related issues involved in designing advanced on-chip interconnect networks.     

基于SOC/IP的智能传感器设计研究

提出了基于SOC/IP的智能传感器的设计方法.在分析传感器IP功能复用基础上,设计了构成智能传感器芯片的数据采集、信号处理、数据通信、人机界面、任务调度等一系列IP核模块.通过在FPGA及ARM7微处理器上的硬件实现仿真,验证了设计方法的正确性.利用IP功能复用,只需重新设置任务调度IP核,就能设计出用于各种传感器的智能化片上系统,构成智能传感器.     

Applications and architectures [microprocessor chips]

Chips are getting more expensive both to design and to manufacture. That makes it tempting for semiconductor companies to push more functions onto a single chip, using software to customize it for specific applications. Using software to customize a few platforms for a variety of applications spreads the mask costs over more chips. It also saves the time of switching from one mask set to another. Time is money, so reducing the variety of parts that require fabrication helps reduce costs in other ways as well. As a result, chip manufacturers try to design platforms that can support a range of products. Customers who buy the chips to build systems use software to customize the functionality.     

一个通用实时多路视频服务器的硬件实现

阐述一个基于DSP的四路实时音视频编码终端的硬件设计方案和实现过程.重点讨论TMS320DM642主处理芯片和音视频处理系统的设计,另外对存储电路,网络接口,ⅡC接口和电源等模块也做了深入讨论.最后对硬件做了信号仿真,指出电路设计和PCB布局布线的关键要点.软件测试结果表明视音频主观质量较优,系统硬件工作稳定可靠,具有通用性.     

IXP425和DM642的会议电视多点控制单元硬件设计

介绍了采用IXP425作为核心主控单元和3片DM642作为核心数据处理单元的会议电视多点控制单元的硬件设计原理和实现方法。主控制器IXP425模块完成网络发送/接收、数据调度、PCI控制等功能。数据处理DM642模块完成音/视频混合与切换等功能。IXP425和DM642之间采用PCI总线连接,各模块之间数据传输速度快,提高了数据处理效率。     

The worst-case chip problem

In the system level, adaptive fault diagnosis problem we must determine which components (chips) in a system are defective, assuming the majority of them are good. Chips are tested as follows: Take two chips, say x and y, and have x report whether y is good or bad. If x is good, the answer is correct, but if x is bad, the answer is unreliable. One way to identify all defective chips is to identify a single good chip which can then be used to diagnose the other chips; the chip problem is to identify a single good chip. We show that the chip problem is closely related to a modified majority problem in the worst case and use this fact to obtain upper and lower bounds on algorithms for the chip problem.     

Guest Editors' Introduction: Hot Interconnects 12

Hot Interconnects is an annual conference that specializes in state-of-the-art hardware and software architectures, and implementations of interconnection networks of all scales, ranging from on-chip, processor-memory interconnects to wide-area networks. It is the event where the high-performance computing and high-speed networking communities meet, and has a wide attendance both from industry and academia. Hot Interconnects 12 convened from 25 to 27 August 2004 at Stanford University; it included two days of paper sessions and one day of tutorials. Sponsored by the IEEE Computer Society Technical Committee on Microprocessors and Microcomputers, Hot Interconnects also has technical cosponsorship from the IEEE Communications Society Technical Committees on High-Speed Networking and Communications Switching and Routing.     

Artificial retina chips for image processing

Artificial retina chips which can simultaneously sense and process real world images are described. The comparison between artificial retinal systems and conventional image processing systems is described. Variable sensitivity photodetection, which is an essential technology for the artificial retina chips, is introduced in detail. The concept, structure, fundamental performance, operating principle, and processing functions for the fabricated artificial retinal chips are described. Applications including interactive games by gesture-input are also introduced. This work was presented, in part, at the International Symposium on Artificial Life and Robotics, Oita, Japan, February 18–20, 1996.     

通信芯片电压故障注入测试与功能安全评估方法

芯片是现代信息技术的核心和基础,芯片的功能安全在确保电子技术的可靠性方面发挥着重要作用。本研究以CAN通信芯片为对象,提出了一种基于电压故障注入的芯片功能安全评估方法。通过基于原型系统的自动化硬件故障注入测试,并结合自动触发信号与控制模块的设计,完善了目前CAN芯片安全性测试技术和功能实现上的不足。另外,基于该CAN芯片测试结果,提出了芯片对故障因素敏感的功能安全评估依据。结果表明,该电路通信芯片的某些管脚对标准工作电压范围下输入电压的幅值、脉宽和延迟毛刺较敏感。测试电路系统能够自动实现1.5~5.5 V大范围工作电压下的随机错误注入,以及错误要素敏感度分析,为提高通信芯片安全性提供更高效的评估依据。     

Influence of tool fabrication process on characteristics of hot embossed polymer microfluidic chips for electrospray

Fabrication techniques for mass manufacture of disposable polymer microfluidic chips are important for electrospray application used in mass spectrometry. Hot embossing offers advantages over traditional MEMS fabrication techniques and is the focus of this research. The aim of the paper is to evaluate hot embossed open channel polymer chips using two different hot embossing tools. One tool was fabricated in nickel using the electroforming process, and the other in high carbon bright steel by laser machining technique using a pulsed Nd:YAG laser that is normally used for conventional applications. Process parameters are determined and measurement of dimensions and surface roughness of tools and chips are presented. Depending on the fabrication method, each tool exhibits its own characteristic profile feature and surface roughness. Polystyrene and polycarbonate substrates embossed with the electroformed tool exhibited lowest surface roughness of 48 nm compared to 450 nm for the laser machined tool. The embossed microfluidic chips were tested for fluid flow and electrospray and showed good performance.     

The LabMatrix system

The LabMatrix^™ is a prototyping system designed to give the user a practical and versatile platform for testing microfluidic applications in the fields of health care and life sciences. The LabMatrix^™ system consists of a microfluidic breadboard and cover that align and secure a series of specially designed LabMatrix^™ microfluidic chips. Chips are easily arranged and rearranged into a user-defined fluidic network. The LabMatrix^™ system is designed with maximum flexibility in mind, providing the user with a means to prototype a wide range of microfluidic applications in a short period.     

SIP多方视频会议系统与原型系统的实现

视频会议系统作为新型多媒体应用的典型代表其研究和应用越来越受到关注.目前IETF所领导的工作组提出XCON会议系统框架以及相关的一些草案.本文介绍XCON会议系统框架,各部分的功能以及涉及的各种协议,并根据多方视频会议系统的需求设计,实现了一个基于XCON框架原型系统.原型系统符合XCON框架,系统可扩展性好,模块之间耦舍度低,安全,能够很好的与其它视频会议系统互操作.