Study of hot-carrier effects on power RF LDMOS device reliability

This paper reports comparative reliability of the hot carrier induced electrical performance degradation in power RF LDMOS transistors after RF life-tests and novel methods for accelerated ageing tests under various conditions (electrical and/or thermal stress): thermal shock tests (TST, air–air test) and thermal cycling tests (TCT, air–air test) under various conditions (with and without DC bias, TST cold and hot, different channel current I_DS and different extremes temperatures ΔT values). It is important to understand the effects of the reliability degradation mechanisms on the S-parameters and in turn on static and dynamic parameters. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are studied by means of 2D ATLAS-SILVACO simulations. The RF performance degradation of hot-carrier effects power RF LDMOS transistors can be explained by the transconductance and miller capacitance shifts, which are resulted from the interface state generation and trapped electrons, thereafter results in a build up of negative charge at Si/SiO₂ interface.     

Radiation-dependent hot-carrier effects

The effect of ionizing radiation on hot-carrier degradation for n-channel MOSFET's has been investigated. It has been experimentally found that hot-carrier degradation for these devices increases after exposure to ionizing radiation. Exposure can be deliberate or occur during device fabrication. The cause of the enhanced degradation has been attributed to radiation-induced trap states.     

MOSFET hot-carrier reliability improvement by forward-body bias

Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impact of substrate bias V/sub SUB/ on hot-carrier reliability is presented. The impact varies with the gate length and body effect factor. These findings are explained, and the effects of future scaling are discussed using a quasi-two-dimensional model. Significant and important improvement in hot-carrier lifetime with forward-bias V/sub SUB/ can be expected for deeply scaled CMOS devices, making it an attractive method for extending the scalability of bulk-Si transistor technology.     

Logic synthesis for reliability: an early start to controllingelectromigration and hot-carrier effects

Designing reliable CMOS chips involves careful circuit design, with attention directed to some of the potential reliability problems such as electromigration and hot-carrier effects. This paper considers logic synthesis to optimize, early in the design phase, against electromigration and hot-carrier degradation. The electromigration and hot-carrier effects are estimated at the gate level using signal activity measure (average number of transitions at circuit nodes). Results on MCNC synthesis benchmarks show that logic can be synthesized to optimize for higher reliability and lower silicon area. A minimum-area circuit is usually not associated with highest reliability     

Simulating IC reliability with emphasis on process-flaw relatedearly failures

A Monte-Carlo reliability simulator for integrated circuits (IC) that incorporates the effects of process flaws, material properties, the mask layout, and use conditions is presented. The mask layout is decomposed into distinct objects, such as contiguous metal runs, vias, contacts, and gate-oxides, for which user-defined distributions are used for determining the failure probability. These distributions are represented by a mixture of defect-related and wearout-related distributions. The failure distributions for nets (sets of interconnected layout objects) are obtained by combining the distributions of their component objects. System reliability is obtained by applying control variate sampling to the logic network which is comprised of all nets. The effects of k-out-of-n substructures within the reliability network are accounted for. The methodology is illustrated by the effect of particulate-induced defects on metal runs and vias in a simple test circuit. The results qualitatively verify the methodology and show that predictions which incorporate failures due to process flaws are appreciably more pessimistic than those obtained from current practice     

Beating the heat [CMOS hot-carrier reliability]

CMOS hot-carrier reliability at both transistor and circuit levels has been examined. Accurate reliability assessment requires defining suitable criteria for acceptable performance for both circuit and individual transistors. As device designers meet demands for greater speed and more complex circuitry accompanied by shrinking the size of transistor into the deep-submicron regime, they have to contend with increase in current densities and higher electric fields. Though in general a MOSFET's driving capability increases as the channel length decreases, the resulting high field will eventually limit the driving capability of the device. The authors discuss improving CMOS hot-carrier reliability through analysis, modelling and simulation     

Analyzing hot-carrier effects on cold CMOS devices

The operation of discrete and integrated CMOS ring oscillators was evaluated over the temperature range 77-300 K. Gate delays typically decreased by a factor of two at 77 K. Hot-carrier effects were enhanced by low-temperature operation, and transistor transconductance degradation occurred at low temperatures, which did not occur at room temperature as measured in the forward and inverse transistor curves. In marked contrast to dc stressing, ac stressing caused very little circuit degradation at low temperatures. By modeling the low-temperature phenomena at the MOSFET source junction, both hot-electron and hot-hole carrier effects were analyzed.     

Direct Monte Carlo simulation of hot-carrier conductivity

We present a Monte Carlo procedure which, by including the mechanism of generation and recombination from impurity centers, enables us to calculate directly from the simulation the field dependent conductivity for the first time. The reliability of the theoretical model has been checked by comparing numerical results with experiments provided by the Montpellier group and performed on p-Si at different acceptor concentrations and temperatures.     

Advanced integrated-circuit reliability simulation includingdynamic stress effects

A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented     

About long-term effects of hot-carrier stress on n-MOSFETS

Transistor characteristics and charge-pumping results obtained during nonuniform long-term hot-carrier stress on n-MOSFETs (no LDD) will be presented. Apart from identifying the overall degradation processes and their drift dynamics, this work focuses on the dependence of the device damage on different stress conditions which are representative for typical applications in the large field of analogue and digital automotive electronic circuits.     

Decoupling of cold-carrier effects in hot-carrier reliability assessment of HfO/sub 2/ gated nMOSFETs

To understand the intrinsic effect of a hot-carrier injection on high-/spl kappa/ dielectrics free from concurrent cold-carrier trapping, the authors have investigated a hot-carrier-induced damage with channel hot-carrier stresses and substrate hot-carrier stress. Compared to substrate hot-carrier stress, the channel hot-carrier stress shows a more significant cold-carrier-injection effect. By using a detrapping bias, they were able to decouple the effect of cold-carrier trapping from the permanent trap generation induced by the hot-carrier injection. As channel hot-carrier stress bias was reduced, a portion of cold-carrier trapping increased and a portion of interface trap generation decreased.     

Improved reliability of bistable circuits by selective hot-carrier stress reduction

The performance and reliability of submicron CMOS circuits have been affected by hot-carrier stress induced degradation. Three common forms of CMOS latch circuits designed using a 0.7-micron commercial process have been considered in a comparative study of the stress levels experienced by individual devices in the circuit. Average stress levels on all the devices over a typical simulation cycle was used to assess the life-time and the reliability of the circuits. We describe a technique that was used to identify the devices having higher than normal stress which may consequently degrade at a faster rate than other devices leading to an early failure of the circuit. We have developed design techniques that can be used to reduce the stress levels in identified devices. The improvements in life-time and reliability have been assessed and analysed. The best circuit configuration to reduce hot-carrier stress induced degradation has been identified.     

Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects

The impact of 3D device architecture in aggressively scaled embedded non-volatile memories has been investigated by means of experiments and 3D TCAD simulations. A complete 3D calibration methodology covering DC and transient operating regimes has been introduced and validated against measurements for different technological options. This approach has been employed to determine the key features for device optimization. In particular, shallow trench isolation corners around the active area have been identified as critical regions of the memory cell for program and erase operations, as well as for gate coupling ratio optimization.     

Numerical simulation of avalanche hot-carrier injection in short-channel MOSFET's

Based on two-dimensional MOSFET simulation, the substrate and gate currents resulting from impact ionization generated electron-hole pairs and their injection into the gate oxide are calculated. The improved injection model uses a nonMaxwellian distribution function and considers separate contributions to the gate current from both thermionic-emission and oxide-barrier tunneling. A fine structure in experimentally observed I/sub g//sup e/ vs. v/sub g/ curves for thin-oxide devices at v/sub g/ approximately=2.3v/sub d/ is simulated. Simulation of a lightly doped drain (LDD) MOSFET also reveals the unusual feature of a double hump in the substrate current and an abrupt increase of the gate current beginning at v/sub g/ approximately=3/2v/sub d/.<>     

Modeling hot-carrier effects in polysilicon emitter bipolartransistors

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by ΔI_B∝I_R ^m+ntⁿ where n≈0.5 and m ≈0.5. The more complex relationships of Δβ(I _C, I_R, t) and β(I _C, I_R, t) result naturally from the simple ΔI_B model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology     

Asymptotic electron energy flux equations for hot-carrier transport simulation

In isothermal device simulations, the Bernoulli function has to be computed carefully to avoid potential numerical difficulties. Problems may arise when the difference in discretized potential values between two nodes is sufficiently small. In nonisothermal hot-carrier transport, additional asymptotic cases can arise depending on the difference in the electron temperature values. In this letter, all possible limiting expressions for the electron energy flux are presented. A parallel treatment will lead to the corresponding equations for current densities.     

Modelling of hot-carrier degradation and its application for analog design for reliability

An analytical CMOS transistor ageing model is presented and a new procedure that allows the extraction of its parameters are presented in this paper. Then, we show how this model can be used to forecast and understand the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the analog designer to choose and/or modify a circuit in order to minimise the hot-carrier induced degradations. Finally, we use an ageing simulation tool realised in VHDL-AMS to validate the analytical study, and we present our first experimental results.     

An improvement of hot-carrier reliability in the stackednitride-oxide gate n- and p-MISFET's

Thin LPCVD stacked nitride-oxide gate MISFET's offer the potential for high current drive as a consequence of the high permittivity of the nitride. However, thin nitride-oxide films have yet to be used in actual MISFET's for LSI products because thin nitride films have poor masking ability during re-oxidation and low reliability under hot-carrier stress. We have investigated improvements to thin LPCVD stacked nitride-oxide films as regards masking ability during re-oxidation and hot-carrier reliability. The method proposed to improve film quality is densification through high-temperature rapid thermal processes and its effectiveness has been tested. Simple rapid thermal annealing (RTA) did not improve the film quality at all. On the other hand, rapid thermal nitridation (RTN) on the deposited nitride film improved it considerably. The reason for the improvement by RTN was investigated     

Performance and hot-carrier effects of small CRYO-CMOS devices

The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a VGnearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and VTshifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides.