基于Landweber迭代算法的欠采样恢复数字预失真技术

传统宽带数字预失真(DPD)为了更好地矫正功率放大器(PA)非线性特性,通常要求反馈通道带宽达到发送信号带宽的5倍,相应地要求更高采样率的模数转换器(ADC),这将导致数字预失真系统面临着硬件成本和能耗问题。针对这一问题,该文提出一种基于Landweber迭代算法的欠采样恢复(USR)数字预失真(Landweber-USR DPD)技术。这种以内外循环的方式进行处理,可将反馈通道带宽从理论要求的5倍降低至2倍,以良好的质量从欠采样的功放输出信号中恢复全频带的输出信号,使还原出的数据更接近真实的功放输出信号,以实现更好的预失真效果。实验选用基于单管氮化镓(GaN)器件的宽带F类功率放大器,在1.8 GHz工作频点下用5 MHz的长期演进(LTE)信号激励,反馈ADC速率分别设置为全采样速率(40 Msps)和欠采样速率(10 Msps)。实验结果充分证明了Landweber迭代算法恢复功放数据的可靠性以及Landweber-USR DPD技术的有效性,为宽带通信系统中数字预失真技术的工程实现提供了有效降低ADC采样率的思路和方法。     

基于Landweber迭代算法的欠采样恢复数字预失真技术

传统宽带数字预失真(DPD)为了更好地矫正功率放大器(PA)非线性特性,通常要求反馈通道带宽达到发送信号带宽的5倍,相应地要求更高采样率的模数转换器(ADC),这将导致数字预失真系统面临着硬件成本和能耗问题.针对这一问题,该文提出一种基于Landweber迭代算法的欠采样恢复(USR)数字预失真(Landweber-USR DPD)技术.这种以内外循环的方式进行处理,可将反馈通道带宽从理论要求的5倍降低至2倍,以良好的质量从欠采样的功放输出信号中恢复全频带的输出信号,使还原出的数据更接近真实的功放输出信号,以实现更好的预失真效果.实验选用基于单管氮化镓(GaN)器件的宽带F类功率放大器,在1.8 GHz工作频点下用5 MHz的长期演进(LTE)信号激励,反馈ADC速率分别设置为全采样速率(40 Msps)和欠采样速率(10 Msps).实验结果充分证明了Landweber迭代算法恢复功放数据的可靠性以及Landweber-USR DPD技术的有效性,为宽带通信系统中数字预失真技术的工程实现提供了有效降低ADC采样率的思路和方法.     

带限DVR数字预失真线性化算法研究

针对信号带宽的增加所导致的数字预失真反馈回路的模数转换器(Analog-to-Digital Converter,ADC)采样率受限的问题,提出了基于带限分解向量旋转(Band Limited De-composed Vector Rotation,BL-DVR)模型的数字预失真模型,从而更好地对宽带功放的非线性引起的...     

一种峰值功率控制的带限数字预失真算法

针对宽带无线通信系统中数字预失真技术反馈回路存在模数转换器ADC的采样速率高、预失真后信号峰均比(PAPR)增大的问题,提出一种结合峰值功率控制的带限数字预失真算法。通过设置阈值门限,对预失真后的信号幅度进行控制以减小其PAPR;运用带通滤波器限制ADC采样带宽并通过频谱外推方法完成对带限输出信号的完整估计,实现ADC采样速率的降低。实验结果表明,该算法不仅能降低系统采样速率,而且能有效提升功放的线性度,相对于传统预失真技术,功放输出信号的邻道功率比改善约5dB。     

基于数/模混合预失真技术的功放线性化北大核心CSCD

随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优势,把模拟预失真和数字预失真融合在一起,共同补偿功放的非线性。由于受实验设备采样率的限制,文中采用了带宽为60 MHz的5 G NR信号对一个中心频率为3.5 GHz的射频功放进行实验验证。实验结果表明:提出的混合预失真器不仅优于单独的数字预失真器和模拟预失真器的非线性矫正性能,而且还能改善数字预失真因采样率限制无法改善的带外互调失真。     

凌力尔特推出14位310Msps双信道ADC系列

凌力尔特公司（Linear Technology）推出双通道（LTC2158—14）和单通道（LTC2153—14）高IF采样14位、310Msps模数转换器（ADC）．这两款器件专为多种带宽数字预失真（DPD）线性化应用而设计。数字预失真是一种闭环反馈系统，在基站发送器输出端对失真带宽采样，并调节输入信号，以消除功率放大器的互调失真分量。这使发送器能以1dB压缩点的最高频率工作，在这种情况下．功率放大器（PA）的响应是非线性的。     

基于改进型径向基函数神经网络的功放线性化

提出了一种基于改进型径向基函数神经网络(MRBFNN)的数字预失真线性化模型,用于更为精确地矫正宽带射频功率放大器的动态非线性。该神经网络模型的输入层使用传统的延时抽头以补偿功放的线性记忆效应,同时对每个抽头进行级数展开用于补偿功放的非线性记忆效应,从而更好地抑制功放的动态非线性失真。文中使用WCDMA 三载波信号对一个460MHz 的Doherty 功率放大器进行数字预失真线性化实验。实验结果表明,与传统数字预失真线性化模型相比,基于改进型径向基神经网络的数字预失真线性化模型能更好地抑制宽带功放动态非线性引起的带外频谱再生,其三阶互调(IMD3)失真最多可以抑制23dB,大大提高了功放的线性度,验证了所提出的数字预失真线性化模型的有效性。     

功放数字预失真技术现状及未来发展

功放是无线通信发射机的重要组成部分,随着无线通信的不断发展,对宽带线性功放的要求也越来越高。然而,功放的非线性特性和记忆效应会导致信号严重失真。为了减小带内失真和邻道干扰,数字预失真成为功放线性化技术中最有发展潜力的技术。介绍了功放模型,数字预失真的学习结构、数字预失真器参数的辨识算法等研究现状,探讨了数字预失真的发展趋势,为今后数字预失真技术的研究提供参考。     

一种基于维度加权盲K近邻算法的数字预失真技术

传统的数字预失真(DPD)模型通常在所有的输入信号功率上采用单一多项式模型和单一记忆深度对功率放大器(PA)进行线性化矫正。然而,功率放大器在不同的功率水平下会呈现出不同的非线性特性,并产生不同的记忆效应。针对这一问题,该文提出一种基于维度加权盲K近邻(KNN)算法的数字预失真模型,所提模型根据功放当前输入信号以及记忆输入信号的幅度进行维度加权的KNN分类,组成维度加权盲KNN记忆多项式(WKMP)模型,并为每一类输入信号序列建立子模型。所提方法用Doherty功率放大器进行实验验证,使用带宽为30 MHz、频点为2.2 GHz的3载波长期演进(LTE)信号作为输入,反馈端使用122.88 MHz的采样率进行采样。实验结果表明,所提维度加权盲KNN分类方法与记忆多项式(MP)模型结合时,功放正向建模效果和数字预失真效果均超过了广义记忆多项式(GMP)模型,并远超记忆多项式模型的效果,实验结果验证了所提模型的优良性能。     

基于增强型LSTM神经网络的5G射频功放线性化

本文提出了一种基于增强型LSTM神经网络(A-LSTM)的数字预失真线性化模型,以更好的补偿5G宽带射频功放的动态非线性特性。模型的输入层在引入延迟抽头模拟功放线性记忆效应的基础上,对每一个延迟抽头进行非线性级数展开用于补偿功放的非线性记忆效应,从而更好地抑制功放的动态非线性失真导致的带内失真以及带外频谱扩展等问题。为验证模型的有效性,本文采用100MHz的5GNR信号作为测试信号,对一个中心频率为2.6GHz的5G射频功放进行数字预失真线性化实验。实验结果表明,基于增强型LSTM神经网络数字预失真器的带外抑制可达16dB,相比于其他几种预失真器展现出更好的线性化效果,验证了基于增强型LSTM神经网络数字预失真器的有效性。     

Exploiting low complex digital predistortion to improve wideband nonlinear satellite downlinks

With the increasing demand for higher data rate, increasing throughput requires wider bandwidth. Due to the nonlinear effect of power amplifier, severe nonlinear distortion effects will appear onboard satellite. Digital predistortion (DPD) scheme is usually employed to compensate for the distortions and memory effects introduced by traveling wave tube amplifier (TWTA) and output multiplexing filter (OMUX). In conventional predistorter, the signal loss of band‐limited feedback signal output through OMUX is usually ignored. Actually, it will affect the linear effect of TWTA. In order to solve the problem as to improve wideband nonlinear satellite downlink, this paper introduces a novel spectral extrapolation method based on deep neural network to recover the band‐limited feedback signal. On this basis, an advanced orthogonal matching pursuit algorithm is adopted in the nonlinear TWTA model construction to further reduce the DPD complexity. The proposed setup effectively compensates the distortions and is well suited for systems that generate data bits on satellites.     

基于低采样率数模转换器和模数转换器的太赫兹发射机线性化

太赫兹(THz)频率高、带宽大,是6G移动通信中极具优势的潜在无线频谱资源。然而太赫兹器件的非线性失真,限制了功率转换效率与通信传输距离。若采用传统数字预失真(DPD)技术对其进行非线性校正,通常要求数模转换器(DAC)和模数转换器(ADC)的采样速率达到信号带宽的5倍,对于太赫兹频段难以应用。因此,该文提出一种低速率DAC和ADC的DPD算法对太赫兹发射机的非线性进行校正。该方法主要分为3个步骤:首先利用低采样率ADC获取的观测数据进行上采样,恢复出带宽受限的高采样率的观测信号,此时信号采样率为信号带宽的5倍,可以有效表征出5阶非线性失真;然后建立带宽受限的DPD模型,采用最小二乘算法提取DPD校正系数;最后对校正后的信号进行下采样送往DAC以校正发射通道的非线性失真。仿真结果表明,当DAC和ADC工作在1.25倍基带信号速率的采样率条件下,对于64-QAM调制信号,该方法可以把误差矢量幅值(EVM)从8.46%降低到2.27%,从而可以支持更高阶的调制方式。     

A Method to Reduce Sampling Rate of the ADC in Feedback Channel for Wideband Digital Predistortion

This paper presents a new digital predistortion (DPD) solution for wideband signals with low feedback sampling rate. To reduce the minimum sampling rate of the analog-to-digital converter (ADC) for wideband digital predistortion, the proposed method uses a bandpass filter to form a narrowband signal before the ADC. Then, a deconvolution operation is performed to recover the original wideband signal from the ADC samples. The proposed method is evaluated with an international mobile telecommunication-advanced signal with 100 MHz bandwidth. The simulation results show that the recovered signal of the proposed method closely approximates to the original signal in the passband of the filter, and the mean square error of the deconvolution decreases as the signal-to-noise ratio increases. The proposed algorithm can reduce the sampling rate of the ADC from 1105.92 million samples per second (MSPS) to 368.64 MSPS, and improve the adjacent channel power ratio more than 20 dB, which is merely 5.6 dB less than the conventional DPD with 1105.92 MSPS sampling rate.     

Adaptive Digital Feedback Predistortion Technique for Linearizing Power Amplifiers

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm     

甚低功耗15Ms/s逐次逼近型ADC的设计实现

采用一种新颖的甚低功耗SAR ADC结构技术,基于SMIC 0.18μm CMOS工艺,设计实现了一个8bit、15Ms/s SAR ADC的芯片电路.该ADC利用电荷分享技术实现数据的采样/保持和逐次逼近转换过程,同时采用了异步时序控制技术代替传统的同步时序控制方式,对SAR控制逻辑进行优化设计,使其在功耗和速度方面都达到优良的性能.仿真结果显示该ADC能在15Ms/s的采样率下正常工作,平均功耗仅为518μW,整体性能优值FOM值达到了0.18pJ/Cony,远低于传统结构.     

环圈行波管设计新进展

本文介绍了环圈行波管设计上的新方法。用这种方法,使频率从2.0～2.5GHz获脉冲输出功率12kW及平均输出功率600W。平均输出功率比国外报道L波段极限400W的水平还高出200W。     

Low sampling rate technique based frequency-domain random demodulation for broadband digital predistortion

This paper proposes a combination technique of the frequency-domain random demodulation (FRD) and the broadband digital predistorter (DPD). This technique can linearize the power amplifiers (PAs) at a low sampling rate in the feedback loop. Based on the theory of compressed sensing (CS), the FRD method preprocesses the original signal using the frequency domain sampling signal with different stages through multiple parallel channels. Then the FRD method is applied to the broadband DPD system to restrict the sampling process in the feedback loop. The proposed technique is assessed using a 30 W Class-F wideband PA driven by a 20 MHz orthogonal frequency division multiplexing (OFDM) signal, and a 40 W GaN Doherty PA driven by a 40 MHz 4-carrier long-term evolution (LTE) signal. The simulation and experimental results show that good linearization performance can be achieved at a lower sampling rate with about 24 dBc adjacent channel power ratio (ACPR) improvement by applying the proposed combination technique FRD-DPD. Furthermore, the performance of normalized mean square error (NMSE) and error vector magnitude (EVM) also has been much improved compared with the conventional technique.     

A 1 Gsps and 840 µW fully dynamic asynchronous pipelined binary search ADC

In this paper a very low power asynchronous 5-bit ADC in CMOS 45 nm process technology is described which combines the pipeline and binary search architectures. Due to utilization of dynamic non-linear amplifier, power consumption of the converter is very low. The ADC circuit uses digital calibration technique to update the reference voltages of the comparators. The power consumption of ADC is 840 µW, and the ENOB is 4.05 at 1 Gsps with input signal at the Nyquist rate. At sampling rate of 10 0Msps, the power consumption is reduced to 89 µW and the ENOB is equal to 4.6 again at the Nyquist rate.