一种高性能宽带LC VCO的设计

基于TSMC 65 nm CMOS工艺,采用电流偏置型差分负阻结构,设计了一个宽频率覆盖范围(7.6 ~ 10.7 GHz)的电感电容谐振压控振荡器(LC VCO)。采用差分控制电压方式,减小共模噪声对VCO性能的影响。采用三组可变电容共同作用的方式,减小VCO增益随振荡频率的变化,同时实现频率的温度补偿。创新性地采用一种新型开关结构,在基本不增加面积的情况下,优化了LC VCO的相位噪声性能。将该LC VCO用于为4.2 ~ 5 GHz双沿采样DAC提供时钟的锁相环电路,实现了良好的相位噪声性能。     

一种高性能宽带LCVCO的设计

基于TSMC 65nm CMOS工艺,采用电流偏置型差分负阻结构,设计了一个宽频率覆盖范围(7.6~10.7GHz)的电感电容谐振压控振荡器(LC VCO)。采用差分控制电压方式,减小共模噪声对VCO性能的影响。采用三组可变电容共同作用的方式,减小VCO增益随振荡频率的变化,同时实现频率的温度补偿。创新性地采用一种新型开关结构,在基本不增加面积的情况下,优化了LC VCO的相位噪声性能。将该LC VCO用于为4.2~5GHz双沿采样DAC提供时钟的锁相环电路,实现了良好的相位噪声性能。     

基于0.18μm SiGe BiCMOS工艺的60GHz VCO分析与设计

采用0.18 μm SiGe BiCMOS工艺,设计了一个60GHz的交叉耦合差分压控振荡器(VCO).通过分析传输线的性能,用λ/ 4短路传输线构造谐振回路.在分析VCO相位噪声的基础上,采用噪声滤波技术提高VCO的相位噪声性能.该VCO的工作电压为2.2V,偏置电流为11mA,频率调谐范围为58.377GHz～60.365GHz.当振荡频率为60.365GHz时,1MHz和10MHz频偏处的相位噪声分别为-79.1dBc/ Hz和-99.77dBc/ Hz.     

一种2.2～5.5G宽带低相位噪声LC VCO设计

论文基于BiCMOS工艺,采用了8个LC VCO并列的工作模式实现了2.2～5.5 GHz的带宽范围的LC VCO,每个LC VCO可以进行单独的调节.在LC VOC的核心电路中采用电阻代替电流镜方式以及在输出处增加了两个三极管限幅,以得到较低的相位噪声.在各个LC VCO的中心频率处其相位噪声优于-96 dBc@100 kHz.当电源电压为5 V时,各个LC VCO的工作电流为3.2 mA～4.2 mA.     

宽带LC压控振荡器的相位噪声优化设计

采用0.35 μm BiCMOS工艺,设计了一款基于开关电容阵列结构的宽带LC压控振荡器.同时分析了电路中关键参数对相位噪声的影响.基于对VCO中LC谐振回路品质因数的分析,优化了谐振回路,提高了谐振回路的品质因数以降低VCO的相位噪声.采用噪声滤波技术,减小了电流源晶体管噪声对压控振荡器相位噪声的影响.测试结果表明,优化后的压控振荡器能够覆盖1.96～2.70 GHz的带宽,频偏为100 kHz和1 MHz的相位噪声分别为-105和-128 dBc/Hz,满足了集成锁相环对压控振荡器的指标要求.     

基于可调谐LC谐振回路的双频VCO

采用嵌有交叉耦合晶体管对的LC谐振回路结构,利用其固有的多种振荡模式,设计了一款用于多标准射频收发器的压控振荡器(VCO)。该电路通过变容管开关偏置的作用,操作于高频串联谐振和低频并联谐振两个模式,并且输出的所有频率都与谐波无关。通过累积型MOS变容管的调谐作用对LC谐振回路的节点阻抗进行改变,实现振荡器在两个模式下的切换。基于TSMC 0. 18μm 1P6M CMOS工艺实现文中所提出的VCO,测试表明:该VCO的振荡频率为2.92 GHz~3.23GHz和7.31 GHz~8.2 GHz,该两个频带的相位噪声分别为-128.22 dBc/Hz@1 MHz和-123.2 dBc/Hz@1 MHz。     

数字电视调谐器中低噪声LC VCO的设计

给出了基于0.25μm CMOS工艺的数字电视调谐芯片中宽带低噪声LC VCO的设计,通过对VCO谐振网络的优化设计,显著抑制了flick噪声对相位噪声的影响,使三个波段的VCO的相位噪声有了明显改善,文中重点讨论了中波段VCO谐振网络的设计方法并给出中波段的相位噪声的仿真和测试结果。结果显示在中波段偏移中心频率10k处的相噪能改善5~10dBc,整个中波段相位噪声低于-85dBc/Hz@10kHz,频率覆盖190~530MHz。     

GPS接收机中1.57 GHz CMOS锁相环的设计

设计了一种用于GPS接收机中采用CMOS工艺实现的1.57GHz锁相环.其中,预分频器采用高速钟控锁存器(LATCH)的结构,工作频率超过2GHz.VCO中采用LC谐振回路,具有4段连续的调节范围,输出频率范围可以达到中心频率的20%.电荷泵采用一种改进型宽摆幅自校准电路,可以进一步降低环路噪声.锁相环采用0.25μmRFCOMS工艺实现.测量表明VCO输出在偏移中心频率1MHz处的相位噪声为-110dBc/Hz,锁相环输出在偏移中心频率10kHz处的相位噪声小于-90dBc/Hz.供电电压为2.5V时,功耗小于15mW.     

4.2GHz 1.8V CMOS LC压控振荡器

基于Hajimiri提出的VCO相位噪声模型,分析了差分LC VCO电路参数对于相位噪声的影响。根据前面的分析,详细介绍了LC VCO电路的设计方法:包括高Q值片上电感的设计、变容MOS管的设计以及尾电流的选取。采用SMIC 0.18μm 1P6 M、n阱、混合信号CMOS工艺设计了一款4.2GHz 1.8V LC VCO。测试结果表明:当输出频率为4.239GHz时,频偏1MHz处的相位噪声为-101dBc/Hz,频率调节范围为240MHz。     

1．3～2．2 GHz低噪声低功耗 CMOS LC VCO的设计

基于TSMC 0．18μm RFCMOS工艺,设计并实现了一个宽带低功耗低相位噪声的高性能压控振荡器（VCO）．为实现1．3～2．2 GHz调谐范围,VCO采用7‐bit（128根调谐曲线）固定电容阵列,同时也获得了超低的增益,降低了相位噪声．为弱化宽调谐范围带来的增益波动,VCO采用3‐bit可变电容阵列来提升低带曲线的斜率,以期与高带一致．为实现每根曲线的宽线性范围,可变电容采用分布式偏置电压技术．为降低相位噪声,还提出了一种输出零偏置架构以及电流源噪声滤除技术．测试结果表明,调谐电压的线性范围为0．2～1．6 V ;VCO输出频率范围为1．3～2．17 GHz ;高带调谐曲线叠合超过50％,低带超过80％;VCO增益仅为19 M Hz／V ;增益波动范围为13～25 M Hz／V ．当振荡频率为1312 M Hz ,1 M Hz 频偏处相位噪声为－116．53 dBc／Hz ;当振荡频率为2152 M Hz ,1 M Hz频偏处相噪为－112．78 dBc／Hz ．VCO功耗电流为1．2～3．2 mA ,电源电压为1．8 V ．提出的VCO既能提供51％的频率覆盖,又能实现低相位噪声,已经被成功应用于工业自动化无线传感网（WIA ）射频收发机芯片中．     

A low power current-reuse LC-VCO with an adaptive body-biasing technique

This work presents a low-power low-phase noise current-reuse LC voltage controlled oscillator (VCO) with an adaptive body-biasing technique that enhances the reliability of the proposed circuit under process, voltage, and temperature (PVT) variations. Furthermore, the supply voltage and power consumption of the proposed VCO are reduced by the start-up oscillation condition that is provided by the adaptive body-biased circuit. This property is in fact very interesting from the power management perspective. The proposed VCO works at carrier frequency of 1.8 GHz and draws the power of only 306 µW from a 0.9 V supply. It achieves phase noise of −123.36 dBc/Hz at 1 MHz offset and provides a figure-of-merit (FoM) of −193.61 dBc/Hz. The post-layout simulation results of designed VCO in 0.18 µm standard CMOS technology confirm the effectiveness of the proposed circuit.     

Low Voltage CMOS LC VCO with Switched Self‐Biasing

This paper presents a switched self‐biasing and a tail current‐shaping technique to suppress the 1/f noise from a tail current source in differential cross‐coupled inductance‐capacitance (LC) voltage‐controlled oscillators (VCOs). The proposed LC VCO has an amplitude control characteristic due to the creation of negative feedback for the oscillation waveform amplitude. It is fabricated using a 0.13 µm CMOS process. The measured phase noise is ‐117 dBc/Hz at a 1 MHz offset from a 4.85 GHz carrier frequency, while it draws 6.5 mA from a 0.6 V supply voltage. For frequency tuning, process variation, and temperature change, the amplitude change rate of the oscillation waveform in the proposed VCO is 2.1 to 3.2 times smaller than that of an existing VCO with a fixed bias. The measured amplitude change rate of the oscillation waveform for frequency tuning from 4.55 GHz to 5.04 GHz is 131 pV/Hz.     

A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration

A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.     

一种带有开关电流源的低相噪压控振荡器

提出一种带有开关电流源的电感电容压控振荡器（LC VCO）。该技术通过反馈电容将电感电容压控振荡器的输出耦合到电流源,形成了电流源的开关特性,从而减小了电感电容压控振荡器的相位噪声。提出的电感电容压控振荡器采用华虹 NEC的0.18μm SiGe BiCMOS工艺,工作频率为5.7 GHz,相位噪声为-113.0 dBc/Hz@1MHz,功耗为2.3 mA。在其他性能相同的情况下,提出的电感电容压控振荡器的振荡频率比典型的电感电容压控振荡器的相位噪声小4.5 dB。     

A 84% tuning range, 4.3-GHz VCO with two-step negative-G<Subscript>m</Subscript> tuning and amplitude calibration loop

This paper presents wideband, low voltage CMOS LC-VCO with automatic two-step amplitude calibration loop to compensate the PVT variation. To cover the wide tuning range, digital automatic negative-G_m tuning loop and analog automatic amplitude calibration loop are proposed. The power consumption is 2–6 mA from a 1.2 V supply. The VCO tuning range is 3.4 GHz, from 2.35 to 5.75 GHz. The measured phase noise is −117 dBc/Hz at the 1 MHz offset when the center frequency is 4.313 GHz.     

宽带低相噪CMOS LC VCO的设计

设计了一款宽带CMOSLCVCO,在分析VCO相位噪声来源的基础上,对VCO进行了结构优化和噪声滤除,并采用了开关电容阵列以增加带宽。电路采用0.18μmCMOS射频工艺进行流片验证,芯片面积为0.4mm×1mm。测试结果显示:芯片的工作频率为3.34～4.17GHz,中心频率为4.02GHz时输出功率是-9.11dBm,相位噪声为-120dBc/Hz@1MHz,在1.8V工作电压下的功耗为10mW。     

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

Wideband Frequency Synthesizer at X/Ku Band by Mixing and Phase Locking of Half Frequency Output of VCO

A wideband low phase noise frequency synthesizer at X/Ku band has been developed by using phase locking and mixing technique at half frequency of voltage controlled oscillator (VCO). The half frequency output signal of the VCO is down converted by a balanced mixer at C band to obtain an intermediate frequency (IF) signal used for phase locking of the VCO. An ultra low phase noise local signal source at 6 GHz is developed with a frequency multiplying chain driven by a 100 MHz oven controlled crystal oscillator (OCXO). Coupling circuit outside the VCO chip to the mixer does not need to be specially designed, which is beneficial to simplify the circuit scheme and improve the phase noise performance. Measurement results show that the phase noise of the output signal at 10.6 GHz to 11.8 GHz and 12.3 GHz to 13.0 GHz is better than −102 dBc/Hz at 10 kHz away form the carrier center. This frequency synthesizer can be used as local signal source or driving source for the development of wideband millimeter-wave frequency synthesizer systems.     

Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193 dBc/Hz. The bandwidth of the frequency is 1.1 GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28 mW under a 1.8 V supply and phase noise is measured as low as −123.6 dBc/Hz at 1 MHz offset under 8.5 GHz oscillation frequencies. This VCO was made by the TSMC 0.18 μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm²).