Glass frit bonding: an universal technology for wafer level encapsulation and packaging

This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass–frit bonding.     

Anodic bonding of glass to aluminium

Anodic bonding of glass to aluminium may provide a higher degree of freedom in device design. In this paper, a systematic variation of the bonding parameters for the aluminium–glass bond is presented. Hermetic seals with strengths of 18.0 MPa can be achieved using a 50–100-nm-thick bonding aluminium layer, and bonding at 300–400°C applying a voltage of 1,000–1,500 V for 20 min. With these parameters, bond yields above 95.1% were obtained on 17 wafers. The bonds survived extensive thermal ageing without significant degradation. The possibility of bonding glass to an aluminium layer with buried, electrically isolated conductors underneath is also demonstrated.     

Wafer-level multilayer integration of RF passives with thick BCB/metal interlayer connection in silicon-based SiP

This paper presents an integration technology for RF passives using benzocyclobutene (BCB)/metal multilayer interconnection for system-in-package applications. This technology has been specially developed for RF subsystem packages in which a thick polymer, BCB (more than 15 μm thick), is adopted as dielectric with lossy silicon as substrate for its excellent characteristics. Both dry-etch BCB and photosensitive BCB are applied in this work, and their processes are briefly introduced and compared. An RF power divider, an MIM capacitor, different types of RF inductors as well as a coupled microstrip based band-pass filter are fabricated and measured at wafer level. The results show good electrical performances, and accordingly the passives are well applicable in RF band. Moreover, the subsystem models including monolithic chips connected with passives are presented.     

BCB contact printing for patterned adhesive full-wafer bonded 0-level packages

Adhesive wafer bonding with a patterned polymer layer is increasingly attracting attention as cheap and simple 0-level packaging technology for microstructures, because the patterned polymer both fulfills the bonding function and determines the volumes between the two wafers housing the devices to be packaged. To be able to pattern a polymer, it has to be cross-linked to a certain degree which makes the material rigid and less adhesive for the bonding afterward. In this paper, a simple method is presented which combines the advantages of a patterned adhesive layer with the advantages of a liquid polymer phase before the bonding. The pattern in the adhesive layer is "inked" with viscous polymer by pressing the substrate toward an auxiliary wafer with a thin liquid polymer layer. Then, the substrate with the inked pattern is finally bonded to the top wafer. Benzocyclobuene (BCB) was used both for the patterned structures and as the "ink". Tensile bond strength tests were carried out on patterned adhesive bonded samples fabricated with and without this contact printing method. The bonding yield is significantly improved with the contact printing method, the fabrication procedure is more robust and the test results show that the bond strength is at least 2 times higher. An investigation of the samples' failure mechanisms revealed that the bond strength even exceeds the adhesion forces of the BCB to the substrate. Furthermore, the BCB contact printing method was successfully applied for 0-level glass-lid packaging done by full-wafer bonding with a patterned adhesive layer. Here, the encapsulating lids are separated after the bonding by dicing the top wafer independently of the bottom wafer.     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Adhesive wafer bonding with photosensitive polymers for MEMS fabrication

Adhesive wafer bonding is a technique that uses an intermediate layer (typically a polymer) for bonding two substrates. The main advantages of using this approach are: low temperature processing (maximum temperatures lower than 400°C), surface planarization and tolerance to particles contamination (the intermediate layer can incorporate particles with the diameter in the layer thickness range). The main bonding layers properties required by a large field of applications/designs can be summarized as: isotropic dielectric constants, good thermal stability, low Young’s modulus, and good adhesion to different substrates. This paper reports on wafer-to-wafer adhesive bonding using SINR^TM polymer materials. Substrate coating process as well as wafer bonding process parameters optimization was studied. Statistical analysis methods were used to show repeatability and reliability of coating processes. Features of as low as 15 μm size were successfully resolved by photolithography and bonded. An unique megasonic-enhanced development process of the patterned film using low cost solvent was established and proven to exceed standard development method performance.     

Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect

In this paper, we developed a hermetic wafer level packaging for MEMS devices. Au–Sn eutectic bonding technology in a relatively low temperature is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of 1 mm × 1 mm × 700 μm, and a square loop Au–Sn metallization of 70 μm in width for hermetic sealing. The robustness of the package is confirmed by several tests such as shear strength test, reliability tests, and hermeticity test. The reliability issues of Au–Sn bonding technology, and copper through-wafer interconnection are discussed, and design considerations to improve the reliability are also presented. By applying O₂ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface. The mechanical effects of copper through-vias are also investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process.     

Wafer-level plasma activated bonding: new technology for MEMS fabrication

Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15–30 min and up to 2–3 h. This new technique enables integration of various materials combinations coming from different production lines.     

MEMS packaging process by film transfer using an anti-adhesive layer

A low cost and low temperature thin film packaging process based on the transfer of an electroplated Nickel 3D cap is proposed. This process is based on adhesion control of a thick molded cap Ni film on the carrier wafer by using a plasma deposited fluorocarbon film, on mechanical debonding and on adhesive bonding of the microcaps on the host wafer with BCB sealing rings. Mechanical characterizations show that the transferred microcaps have a high stiffness, a low stress and a high adhesion. Because this process is simple and only involves a low temperature (250°C) heating of the host wafer, it is highly versatile and suitable for the encapsulation of micro and nano devices, circuits and systems elaborated on a large range of substrate materials.     

A new approach for handling and transferring of thin semiconductor materials

 Based on the fracture mechanics analysis of crack propagation, the phenomenon of subcritical crack growth was utilized for a controlled debonding of directly wafer-bonded interfaces. The approach allowed the well-defined separation of bonded wafers although the bond strength was high due to thermal annealing. The achieved splitting velocity depended on the wafer material, the wafer thickness ratio, the bonding process parameters, and the environmental conditions during cleaving. In combination with wafer bonding, the method can be used for a temporary stiffening and handling of thin and brittle wafers during fabrication, even if the wafers are exposed to high process temperatures. The approach can also be applied to fabricate micromechanical systems (MEMS). Received: 12 July 2001/Accepted: 26 February 2002 This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

Interfacing microfluidics to LDI-MS by automatic robotic spotting

We developed a method of interfacing microfluidics with mass spectrometry (MS) using a robotic spotting system to automate the contact spotting process. We demonstrate that direct and automated spotting of analyte from multichannel microfluidic chips to a custom microstructured MALDI target plate was a simple, robust, and high-throughput method for interfacing parallel microchannels using matrix-assisted laser desorption/ionization mass spectrometry (MALDI-MS). Using thermoplastic cyclic olefin copolymer (COC) polymer microfluidic chips containing eight parallel 100 μm × 46 μm microchannels connected to a single input port, spotting volume repeatability and MALDI-MS signal uniformity are evaluated for a panel of sample peptides. The COC microfluidic chips were fabricated by hot embossing and solvent bonding techniques followed by chip dicing to create open ends for MS interfacing. Using the automatic robotic spotting approach, microfluidic chip-based reversed-phase liquid chromatography (RPLC) separations were interfaced with electrochemically etched nanofilament silicon (nSi) target substrate, demonstrating the potential of this approach toward chip-based microfluidic separation coupled with matrix-free laser desorption/ionization mass spectrometry.     

Low-temperature anodic bonding of silicon to silicon wafers by means of intermediate glass layers

Silicon wafers have been anodically bonded to sputtered lithium borosilicate glass layers (Itb 1060) at temperatures as low as 150–180 °C and to sputtered Corning 7740 glass layers at 400 °C. Dependent on the thickness of the glass layer and the sputtering rate, the sputtered glass layers incorporate compressive stresses which cause the wafer to bow. As a result of this bowing, no anodic bond can be established especially along the edges of the silicon wafer. Successful anodic bonding not only requires plane surfaces, but also is determined very much by the alkali concentration in the glass layer. The concentration of alkali ions as measured by EDX and SNMS depends on both the sputtering rate and the oxygen fraction in the argon process gas. In Itb 1060 layers produced at a sputtering rate of 0.2 nm/s, and in Corning 7740 layers produced at sputtering rates of 0.03 and 0.5 nm/s, respectively, the concentration of alkali ions in the glass layers was sufficiently high, at oxygen partial pressures below 10^-4 Pa, to achieve anodic bonding. High-frequency ultrasonic microanalysis allowed the bonding area to be examined non-destructively. Tensile strengths between 4 and 14 MPa were measured in subsequent destructive tensile tests of single-bonded specimens.     

A MEMS guide plate for a high temperature testing of a wafer level packaged die wafer

This paper describes the design and fabrication of a MEMS guide plate, which was used for a vertical probe card to test a wafer level packaged die wafer. The size of the fabricated MEMS guide plate was 10.6 × 10.6 cm. The MEMS guide plate consisted of 8,192 holes to insert pogo pins, and four holes for bolting between the guide plate and the housing. To insert pogo pins easily, an inclined plane was defined at the back of each hole. Pitch and diameter of the hole were 650 and 260 μm, respectively. In order to define inserting holes and inclined planes at an exact position, silicon MEMS technology was used such as anisotropic etching, deep reactive etching and more. Silicon was used as the material of the guide plate to reduce alignment mismatch between the pogo pins and solder bumps during a high temperature testing. A combined probe card with the fabricated MEMS guide plate showed good x–y alignment and planarity errors within ±9 and ±10 μm at room temperature, respectively. In addition, x–y alignment and planarity are ±20 and ±16 μm at 125°C, respectively. The proposed MEMS guide plate can be applied to a vertical probe card for burn-in testing of a wafer level packaged die wafer because the thermal expansion coefficient of the MEMS guide plate and die wafer is same.     

Low-cost,rapid-prototyping of digital microfluidics devices

An innovative and simple microfabrication method for digital microfluidics is presented. In this method, devices are formed from copper substrates or gold compact disks using rapid marker masking to replace photolithography. The new method is capable of forming devices with inter-electrode gaps as small as 50 μm. Saran™ wrap (polyethylene film) and commercial water repellants were used as dielectric and hydrophobic coatings, respectively, to replace commonly used and more expensive materials such as parylene-C and Teflon-AF. Devices formed by the new method enabled single- and two-plate actuation of droplets with volumes of 1–12 μL. Fabricated devices were successfully tested for droplet manipulation, merging and splitting. We anticipate that this fabrication method will bring digital microfluidics within the reach of any laboratory with minimal facilities. Electronic supplementary material The online version of this article (doi:) contains supplementary material, which is available to authorized users.     

A continuous-membrane micro deformable mirror based on anodic bonding of SOI to glass wafer

As one of the most important components in adaptive optics, the deformable mirror (DM) is required to have a flat surface for better performance. For micromachined DMs, single-crystal-silicon (SCS) membrane is an ideal material for high quality reflective mirror surface owing to its good flatness and small residual stress. In this research, a process was established to realize SCS mirror membrane by DRIE of SOI wafer and anodic bonding of SOI wafer to Pyrex 7740 glass. Using this process, the proof-of-concept for a micromachined DM composed of SCS mirror surface has been successfully demonstrated. The prototype DM shows a stroke of 4.23 μm at 120 V. The P–V and rms of the reflective mirror surface are 492 and 82 nm, respectively. The performance of the prototype DM can somewhat satisfy the need of AO in visible spectrum. Better surface quality is anticipated by employing SOI wafers with strictly controlled residual stress.     

High performance suspended spiral inductor and band-pass filter by wafer level packaging technology

Suspended inductors and 2.45 GHz BPF with patterned ground shields on the lossy silicon substrate by using Cu/BCB based wafer level packaging and bulk Si etching technologies were fabricated. Thick BCB interlayer is used as the supporting dielectric and the backside cavity is easily removed by using a two-step back-etching process. The fabricated 2.7 nH inductor has a maximum Q factor 49 at 8.2 GHz and high Q factors more than 22 in the broadband frequency range from 1 to 10 GHz. And the realized 2.45 GHz BPF has the insertion loss of 3.0 dB and the return loss of more than 14 dB at the pass band. It is also featured by more than 48 and 25 dB attenuation at 0.9 and 1.8 GHz respectively, with the second harmonic rejection being 33 dB.

     

Research on forming and application of U-form glass micro-nanofluidic chip with long nanochannels

The forming process of U-form glass micro-nanofluidic chip with long nanochannels is presented in this paper, in which the fabrication of channels and the assembly of plates are included. The micro-nanofluidic chip is composed of two glass plates in which there are microchannels and nanochannels, respectively. This chip can be used for trace sample enrichment, molecule filtration, and sample separation, etc. In fabrication process, the two-step photolithograph on one wafer is often required in early papers, as nano and micro structure designed in one plate have different depths. In this paper, the channels in micro-nanofluidic chip are designed in two glass plates instead of in one wafer. The nanochannels and microchannels are, respectively, formed on plates using wet etching and two-step photolithograph on one wafer is not required. Since the channels are formed, the upper plate and the bottom plate are assembled together by alignment, preconnection and thermal bonding orderly. Firstly these plates are aligned with the cross-marks on an inverted microscope. The aqueous film between plates is controlled to decrease the static friction force for accurate adjustment. Then the adhesion strength of connection is enhanced with semi-dry status for limiting movement from slight inclining and shaking. At last, the bottom plate and the upper one are irreversibly linked together with thermal bonding. The heating period and max temperature of thermal bonding are optimized to eliminate thermal stress gradient and the size shrinking. With the micro-nanofluidic chip, the 1 μM fluorescein isothiocyanate in 10 mM PBS buffer is concentrated successfully. The sample concentrating factor of light intensity varies from 2.2 to 8.4 with applied voltages between 300 and 2,000 V. The switch effect and the instability effect in concentrating process are described and analyzed too.     

Fabrication method of spacers with high aspect ratio – Used in a field emission display (FED)

Glass to glass anodic bonding using a metal interlayer was used to develop a fabrication method of spacer for field emission display (FED). In this paper, spacers with width 100 μm and height 1000 μm and a 3.54 inch mono color anode plate patterned with Al/Cr film as an interlayer were bonded by the anodic bonding. To bond the spacers on the anode plate vertically, two types of spacer holders were designed and fabricated with photoetchable glass and n(110) Si wafer. The spacer holder using Si wafer was used to fabricate for evacuated FED panel. Received: 22 November 1999/Accepted: 27 January 2000     

Filling of very deep, wide trenches by BenzoCycloButene polymer

A process for deep trench filling by BenzoCycloButene (BCB) polymer is explored. Deep trenches with 100-μm depth and different aspect ratios from 1.4 to 20 have been successfully filled by BCB. Besides, chemical mechanical polishing (CMP) of BCB is studied with the main goals of smoothing surface topography of substrate after BCB filling and removing excess BCB coating which may be necessary in some applications. Removal rate for BCB, V _RR, of about 0.24 μm/min has been achieved for hard cured BCB films using acid slurry. After CMP, the BCB layer showed a roughness of about 1.36 nm (Rq, measured by atomic force microscopy, AFM).