A comprehensive study of hot-carrier induced interface and oxidetrap distributions in MOSFETs using a novel charge pumpingtechnique

A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N_it) and oxide (N_0t) traps in hot-carrier stressed MOSFETs. Direct separation of N_it and N_0t is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms     

Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges

As the channel length rapidly shrinks down to the nanoscale regime, the multiple gate MOSFETs structures have been considered as potential candidates for a CMOS device scaling due to its good short-channel-effects (SCEs) immunity. Therefore, in this work we investigate the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using an analytical analysis of the two dimensional Poisson equation in which the hot-carrier induced interface charge effects have been considered. Basing on this analysis, we have found that the degradation becomes more important when the channel length gets shorter, and the minimum surface potential position is affected by the hot-carrier induced localized interface charge density. Using this analysis, we have studied the scaling limits of DG and GAA MOSFETs and compared their performances including the hot-carrier effects. Our obtained results showed that the analytical analysis is in close agreement with the 2-D numerical simulation over a wide range of devices parameters. The proposed analytical approach may provide a theoretical basis and physical insights for multiple gate MOSFETs design including the hot-carrier degradation effects.     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).     

Increased hot-carrier effects using SiGe layers in verticalsurrounding-gate MOSFETs

The use of silicon germanium (SiGe) heterostructures in vertical surrounding gate MOSFETs provides an additional means for tailoring current-voltage (I-V) characteristics by controlling physical effects inside the device. Incorporation of an SiGe layer in the vertical MOSFET drain can modify hot-carrier characteristics via material dependent impact ionization coefficients. MOSFETs with ramped SiGe drain layers showed increased drain current in the soft breakdown regime, due to increased impact ionization as verified by substrate current measurement, with up to 1.5 V decreases in breakdown voltage. Comparison of simulation to experiment displayed the difficulties of accurately predicting device parameters, but demonstrated the usefulness of simulation to qualitatively predict device behavior without costly expenditures of time, material, and equipment     

Device scaling limits of Si MOSFETs and their applicationdependencies

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications     

Profiling of stress induced interface states in short channel MOSFETs using a composite charge pumping technique

The charge pumping phenomenon is studied and the limits of validity of different experimental alternatives are analysed, taking into consideration emission processes and short channel effects. As a result, a composite charge pumping technique, which can accurately give the energy distribution of interface state densities in short channel MOSFETs, is proposed. The experiment is based on the successive variation of the gate voltage pulse parameters (top and bottom levels, rise and fall times) at room and low temperatures. This method is then applied to study aging effects due to channel hot electron injection. The comparison of the experimental energy profile determined before and after electrical stress shows a global increase of interface states, which is more pronounced near the conduction band edge.     

Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress     

AC hot-carrier effects in MOSFETs with furnaceN2O-nitrided gate oxides

AC hot-carrier effects in n-MOSFETs with thin (~85 Å) N₂O-nitrided gate oxides have been studied and compared with control devices with gate oxides grown in O₂. Results show that furnace N₂O-nitrided oxide devices exhibit significantly reduced AC-stress-induced degradation. In addition, they show weaker dependences of device degradation on applied gate pulse frequency and pulse width. Results suggest that the improved AC-hot-carrier immunity of the N₂O-nitrided oxide device may be due to the significantly suppressed interface state generation and neutral electron trap generation during stressing     

AC versus DC hot-carrier degradation in n-channel MOSFETs

The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three damage mechanisms occurring during both DC and AC operation: interface states created at low and mid-gate voltages, oxide electron traps created under conditions of hole injection into the oxide, and oxide electron traps created under conditions of hot-electron injection. It is shown that the quasi-static contributions of these mechanisms fully account for hot-carrier degradation under AC stress. The AC stress model is applied to devices from several different technologies and to several different AC stress waveforms. Excellent agreement is obtained in each case. The results demonstrate the validity of the model for frequencies up to 1 MHz. The absence of any transient effect indicates that the model could be applicable at much higher frequencies     

Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrierluminescence techniques

This paper addresses the problem of hot-carrier degradation and lifetime monitoring in SOI MOSFETs by means of hot-carrier-induced luminescence measurements. The peculiar emission behavior of SOI devices is clarified over a broad range of bias conditions by means of comparison with that of BULK MOSFETs. It is shown that detailed analysis of hot-carrier luminescence measurements at different photon energies provides a noninvasive monitoring tool for various aspects of degradation, such as worst case bias conditions, threshold voltage shift, and variations of the electric field and hot-carrier population in the damaged region. The measured light intensity represents also a sensitive acceleration factor for the extrapolation of lifetimes to real operating conditions     

Suppression of hot-carrier degradation in Si MOSFETs by germaniumdoping

Presently there are two approaches to the reduction of hot-carrier effects in Si MOSFETs: the use of lightly-doped-drain/double-diffused-drain (LDD/DDD) structures and the reduction of applied bias. Both of these suffer certain penalties. A technique for incorporating Ge impurities in the channel that creates additional scattering so that `lucky' hot carriers are less probable is introduced. Results indicate that while the initial MOSFET characteristics are maintained, the degradation rate under voltage stress is much reduced     

Quantifying self-heating effects with scaling in globally strained Si MOSFETs

Electrical results are presented for deep submicron strained Si MOSFETs fabricated on both thick and thin SiGe strain relaxed buffers, SRBs. For the first time thin SRB devices are shown to offer the same performance enhancements as thick SRB devices. The reduction in performance enhancement with device scaling widely reported in the literature has also been investigated. Correcting for dynamic self-heating effects using ac measurements, the enhancements seen in long channel devices are maintained down to short channel lengths, demonstrating the scalability of SRB technology. Thermal resistances have been measured experimentally and compared with analytical models. The thermal resistance for devices on the thin SRBs is reduced by 50% compared with devices on thick SRBs. Finally, a comparison of self-heating effects in MOSFETs fabricated on SOI and Si_0.8Ge_0.2 SRBs provides insight into the challenges ahead as power densities continue to increase.     

A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz     

The effect of channel hot-carrier stressing on gate-oxide integrityin MOSFETs

The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., ΔV_T and ΔI _D) have become intolerably degraded. In the extreme cases of stressing at V_G≈V_T with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

Hall mobility in hafnium oxide based MOSFETs: charge effects

The Hall effect is used to measure the electron mobility in HfO/sub 2/ based n-channel field effect transistors with poly-Si gates. Large deviations between measured Hall and drift mobilities are explained by the presence of high concentrations of nonfixed charge (up to 4/spl times/10/sup 12/ cm/sup -2/). Simulated mobility curves show that the observed concentrations of fixed and nonfixed charge can estimate the measured mobility significantly better than if only the fixed charge concentration is used.     

1/f noise in hot-carrier damaged MOSFET's: effects ofoxide charge and interface traps

The 1/f noise in the drain current of hot-carrier damaged MOSFETs biased in weak inversion has been studied. By the use of a biased annealing treatment to simultaneously decrease the density of oxide trapped charge (N_ot) and increase the density of interface traps (D_it), the authors have separated the contributions of these two kinds of defects. The results clearly indicate that, while the low-frequency 1/f noise is correlated with N_ot, the high-frequency 1/f noise is correlated with D_it     

Double-pulse charge pumping in MOSFETs

A double-pulse charge-pumping (DPCP) method is described. The method enables measuring of an energy distribution of interface states in both the lower and upper halves of bandgap and allows determination of capture cross section energy distribution for electrons in the upper half of the bandgap in n-channel MOSFETs and for holes in the lower half in p-channel MOSFETs. The method supplements the CP method's family. Its major advantage consists in enhanced immunity against the parasitic geometrical components of the CP current     

Minimized constrains for lateral profiling of hot-carrier-induced oxide charge and interface traps in MOSFETs

For better understanding the hot-carrier-induced reliability problems, a charge-pumping technique has been developed to profile the Q/sub ot/ and N/sub it/ directly from the experimental results. However, the key neutralization condition is acquired by trial and error, which takes much time and effort. Therefore, a technique of two-step neutralization is proposed to find out the appropriate neutralization condition in this work. This two-step neutralization combined with the error-reduction method is shown to carry out the profiling more quickly and precisely.